MC7447AHX1000NB Freescale Semiconductor, MC7447AHX1000NB Datasheet - Page 26

IC MPU RISC 1000MHZ 360-FCCBGA

MC7447AHX1000NB

Manufacturer Part Number
MC7447AHX1000NB
Description
IC MPU RISC 1000MHZ 360-FCCBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC7447AHX1000NB

Processor Type
MPC74xx PowerPC 32-Bit
Speed
1.0GHz
Voltage
1.1V
Mounting Type
Surface Mount
Package / Case
360-FCCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-

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Pinout Listings
26
VDD_SENSE
Notes:
1. OV
2. Unused address pins must be pulled down to GND and corresponding address parity pins pulled up to OV
3. These pins require weak pull-up resistors (for example, 4.7 KΩ ) to maintain the control signals in the negated state after they
4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going
5. This signal must be negated during reset, by pull-up resistor to OV
6. Internal pull up on die.
7. Ignored in 60x bus mode.
8. These signals must be pulled down to GND if unused, or if the MPC7447A is in 60x bus mode.
9. These input signals are for factory use only and must be pulled down to GND for normal machine operation.
10.This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect performance.
11.These signals are for factory use only and must be left unconnected for normal machine operation. Some pins that were
12.These input signals are for factory use only and must be pulled up to OV
13.This pin can externally cause a performance monitor event. Counting of the event is enabled through software.
14.This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation.
15.These pins were NCs on the MPC7447, MPC7445, and MPC7441. They may be left unconnected for backward compatibility
16.These pins were OV
17.These pins provide connectivity to the on-chip temperature diode that can be used to determine the die junction temperature
18.These pins are internally connected to V
19.These pins are internally connected to GND and are intended to allow an external device to detect the processor ground
PLL (after filtering to become AV
HRESET or OV
settings may change in future products, it is recommended BVSEL be configured using resistor options, jumpers, or some
other flexible means, with the capability to reconfigure the termination of this signal in the future if necessary. For actual
recommended value of V
have been actively negated and released by the MPC7447A and other bus masters.
high.
ensure proper operation.
NCs on the MPC7447, MPC7445, and MPC7441 have now been defined for other purposes.
with these devices, but it is recommended they be connected in new designs to facilitate future products. See
“Connection Recommendations,”
are intended to allow an external device to detect the I/O voltage level present inside the device package. If unused, they
must be connected directly to OV
of the processor. These pins may be left unterminated if unused.
level present inside the device package. If unused, they must be connected directly to V
voltage level present inside the device package. If unused, they must be connected directly to GND or left unconnected.
Signal Name
DD
supplies power to the processor bus, JTAG, and all control signals; V
DD
Table 12. Pinout Listing for the MPC7447A, 360 HCTE Package (continued)
G13, N12
(selects 2.5 V); see
DD
pins on the MPC7447, MPC7445, and MPC7441. These pins are internally connected to OV
in
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
or supply voltages see
DD
DD
for more information.
). To program the I/O voltage, connect BVSEL to either GND (selects 1.8 V), or to
or left unconnected.
Table
Pin Number
DD
and are intended to allow an external device to detect the processor core voltage
3. If used, the pull-down resistor should be less than 250 Ω. Because these
Table
4.
DD
or negation by ¬HRESET (inverse of HRESET), to
DD
DD
Active
for normal machine operation.
supplies power to the processor core and the
DD
I/O
or left unconnected.
Freescale Semiconductor
I/F Select
N/A
DD
.
Section 9.4,
1
DD
Notes
18
and

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