MPC8560PX833LB Freescale Semiconductor, MPC8560PX833LB Datasheet

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... MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual. To locate any published errata or updates for this document, contact your Freescale sales office. © 2010 Freescale Semiconductor, Inc. All rights reserved. Document Number: MPC8560EC Rev. 5, 05/2010 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 ...

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... Figure 1. MPC8560 Block Diagram Figure 1 shows the major 256-Kbyte L2-Cache/ SRAM e500 Core 32-Kbyte L1 32-Kbyte L1 I Cache D Cache Core Complex Bus RapidIO-8 RapidIO Controller 16 Gb/s PCI 64b PCI Controller 133 MHz DMA Controller 10/100/1000 MAC MII, GMII, TBI, RTBI, RGMIIs 10/100/1000 MAC Freescale Semiconductor ...

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... ISDN primary rate – Freescale interchip digital link (IDL) – General circuit interface (GCI) — User-defined interfaces — Eight independent baud rate generators (BRGs) — Four general-purpose 16-bit timers or two 32-bit timers MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Overview 3 ...

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... Four banks of memory supported, each Gbyte — DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports — Full ECC support — Page mode support ( simultaneous open pages) MPC8560 Integrated Processor Hardware Specifications, Rev Freescale Semiconductor ...

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... Four global high resolution timers/counters that can generate interrupts — Supports 22 other internal interrupt sources — Supports fully nested interrupt delivery — Interrupts can be routed to external pin for external processing MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Overview 5 ...

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... Buffer descriptors are backward compatible with MPC8260 and MPC860T 10/100 programming models — 9.6-Kbyte jumbo frame support — RMON statistics support — 2-Kbyte internal transmit and receive FIFOs MPC8560 Integrated Processor Hardware Specifications, Rev addressing mode 2 C interface Freescale Semiconductor ...

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... Fully static 1.2-V CMOS design with 3.3- and 2.5-V I/O — Supports power saving modes: doze, nap, and sleep — Employs dynamic power management, which automatically minimizes power consumption of blocks when they are idle. MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Overview 7 ...

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... For devices rated at 667 and 833 MHz For devices rated at 1 GHz For devices rated at 667 and 833 MHz For devices rated at 1 GHz 1 Symbol Max Value Unit –0.3 to 1.32 –0 –0.3 to 1.32 –0.3 to 1.43 GV –0 Freescale Semiconductor Notes — — — ...

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... If the items on line 2 must precede items on line 1, ensure that the delay does not exceed 500 ms and the power sequence is not done more than once per day in a production environment. MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor 2 C, and JTAG I/O voltage 2 ...

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... C, and JTAG signals DD Table 2 are Recommended Symbol Unit Value 1.2 V ± 1.3 V ± 1.2 V ± 1.3 V ± 2.5 V ± 125 3.3 V ± 165 2.5 V ± 125 mV OV 3.3 V ± 165 GND GND REF DD/2 LV GND GND ° 105 j Freescale Semiconductor ...

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... I/O supply voltage. OV appropriate LVCMOS type specifications. The DDR SDRAM interface uses a single-ended differential receiver referenced the externally supplied MV the SSTL2 electrical signaling standard. MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor + 20 GND Not to Exceed 10% ...

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... MPC8560 Integrated Processor Hardware Specifications, Rev (Min) +7 (Max (Max) 62.5 ns +3.6 V –3.5 V Table 3. Output Drive Capability Programmable Output Impedance (Ω (default (default N/A 7.1 V p-to-p (Min) 7.1 V p-to-p (Min) Supply Voltage Notes 2.5 V — 3.3 V — 2.5/3.3 V — 3.3 V — DD — Freescale Semiconductor ...

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... The nominal recommended V is 1.3 V for this speed grade. DD The estimated power dissipation on the AV Notes MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor supply for the MPC8560 is shown in DD Table 4. MPC8560 V Power Dissipation DD 3,4 Typical Power 5.1 5 ...

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... V) Units Notes DD — — — — — — — — — — — — — — — 40 — — — — — — — — Freescale Semiconductor ...

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... This represents the total input jitter—short term and long term—and is guaranteed by design. 5. For spread spectrum clocking, guidelines are +/-1% of the input frequency with a maximum of 60 kHz of modulation regardless of the input frequency. MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor ...

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... Unit 125 — MHz 8 — ns — ns 0.75 1 — =2.5V, and from 0.6 and 2.7V for DD Typical Max Unit — — MHz — — Typical Max Unit Notes — — ns — — — ns — Freescale Semiconductor Notes — — Notes — — 1 ...

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... The CCB clock is determined by the SYSCLK × platform PLL ratio. 6 DDR SDRAM This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the device. MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Table 12. PLL and DLL Lock Times Min — 7680 122,880 ...

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... DIO = 2.5 V ± 0.125 MHz 25° Max Unit 2.625 V 0.51 × 0.04 V REF – 0.18 V REF μA 10 — mA — mA μA 100 Min Max Unit — 0 /2, V (peak to peak) = 0.2 V. OUT DD OUT Freescale Semiconductor Notes — — — . MCK . MCK Notes 1 1 ...

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... DDR SDRAM interface with the DDR DLL enabled. Table 16. DDR SDRAM Output AC Timing Specifications–DLL Mode At recommended operating conditions with GV Parameter MCK[n] cycle time, (MCK[n]/MCK[n] crossing) On chip Clock Skew MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor of 2.5 V ± 5%. DD Symbol Min V — ...

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... DDR timing (DD) from the rising edge of the MSYNC_IN DDSHMP Max Unit — 4.0 ns MCK — ps — ps 0.75 × 1.5 + 4.0 ns MCK 4.0 ns memory clock reference MCK /2. DD describes the DDR timing (DD) DDSHMH can be modified through DDSHMH and t DDSHMP DDSHME follows the symbol DDSHMP Freescale Semiconductor Notes for ...

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... DDR controller for various loadings. These numbers are the result of simulations for one topology. The delay numbers will strongly depend on the topology used. These delay numbers show the total delay for the address and command to arrive at the DRAM devices. The actual delay could be MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor = 50 Ω Figure 5 ...

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... DD OL Input high voltage MPC8560 Integrated Processor Hardware Specifications, Rev Load 20. The potential applied to the input of a GMII,MII, TBI, RGMII, or RTBI Symbol –4.0 mA 4.0 mA Delay Unit 3.0 ns 3.6 ns 5.0 ns 5.2 ns Min Max Unit 3.13 3.47 2. 0.3 DD GND 0.50 1. 0.3 DD Freescale Semiconductor ...

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... Table 21. GMII Transmit AC Timing Specifications At recommended operating conditions with LV Parameter/Condition GTX_CLK clock period GTX_CLK duty cycle GMII data TXD[7:0], TX_ER, TX_EN setup time GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor symbol referenced in IN ...

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... DD 1 Symbol t GRX t /t GRXH GRX t GRDVKH t GRDXKH Min Typ Max — — 1.0 symbolizes GMII GTKHDV symbolizes GMII transmit timing (GT) with respect t GTXR Min Typ Max — 8.0 — 40 — 60 2.0 — — 0.5 — — Freescale Semiconductor Unit ns Unit ...

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... Guaranteed by design. Figure 8 provides the AC test load for TSEC. Output Figure 9 shows the GMII receive AC timing diagram. RX_CLK RXD[7:0] RX_DV RX_ER MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor of 3.3 V ± 5 =2.5V ± 5 Symbol GRXR GRXF (first two letters of functional block)(signal)(state) (reference)(state) for outputs ...

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... MII(M) transmit (TX) clock. For rise and fall times, the latter MTX t MTX t t MTXH MTXF t MTKHDX Figure 10. MII Transmit AC Timing Diagram Min Typ Max — 400 — — 40 — 35 — 1.0 — 4.0 symbolizes MII MTKHDX t MTXR Freescale Semiconductor Unit ...

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... R (rise (fall). 2. Signal timings are measured at 0.7 V and 1.9 V voltage levels. 3. Guaranteed by design. Figure 11 shows the MII receive AC timing diagram. RX_CLK RXD[3:0] RX_DV RX_ER MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor of 3.3 V ± 5 =2.5V ± 5 Symbol 3 t MRX ...

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... TBI transmit timing (TT) with respect to the time from t t TTX t TTXH t TTXF t TTKHDV Figure 12. TBI Transmit AC Timing Diagram Min Typ Max — 8.0 — 40 — 60 2.0 — — 1.0 — — — — 1.0 symbolizes the TBI TTKHDV (K) going high TTX t TTXR t TTKHDX Freescale Semiconductor Unit ...

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... R (rise (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX). 2. Signal timings are measured at 0.7 V and 1.9 V voltage levels. 3. Guaranteed by design. Figure 13 shows the TBI receive AC timing diagram. RX_CLK1 RCG[9:0] RX_CLK0 MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor of 3.3 V ± 5 =2.5V ± 5 Symbol t TRX t ...

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... SKRGT 6 t RGT RGTH RGT RGTH RGT 6 RGTR RGTF represents the TBI (T) receive (RX) clock. Note also that the RGT Min Typ Max –500 0 500 1.0 — 2.8 7.2 8.0 8 — — 0.75 of the lowest speed transitioned RGT Freescale Semiconductor Unit ...

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... Table 28. MII Management DC Electrical Characteristics Parameter Supply voltage (3.3 V) Output high voltage (OV = Min Output low voltage (OV = Min Input high voltage Input low voltage MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor t RGTH t SKRGT TXD[8:5] TXD[3:0] TXD[7:4] TXD[9] TXD[4] TXEN TXERR RXD[8:5] ...

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... Table 1 and Table 2. Typ Max Unit — 10.4 MHz — 1120 ns — — ns — 2*[1/(f /8)] ns ccb_clk — 2*[1/(f /8)] ns ccb_clk — — ns — — ns — — symbolizes MDKHDX Freescale Semiconductor Notes 2, 4 — — — — ...

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... MPC8560 with the DLL enabled. Table 31. Local Bus General Timing Parameters—DLL Enabled Parameter Local bus cycle time LCLK[n] skew to LCLK[m] or LSYNC_OUT MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor t MDC t t MDCF MDCH ...

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... TSEC2_TXD[6: (default) TSEC2_TXD[6: LBKHOX2 TSEC2_TXD[6: (default) TSEC2_TXD[6: LBKHOZ1 TSEC2_TXD[6: (default) Min Max Unit Notes 1.8 — 1.7 — 0.5 — 1.0 — 1.5 — — 2 3.5 — 2 3.7 — 2 3.8 — 2 0.7 — 1.6 0.7 — 1.6 — 2 3.8 Freescale Semiconductor ...

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... LUPWAIT) LUPWAIT input hold from local bus clock LALE output transition to LAD/LDP output transition (LATCH hold time) Local bus clock to output valid (except LAD/LDP and LALE) MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor POR Configuration Symbol TSEC2_TXD[6: LBKHOZ2 TSEC2_TXD[6: (default) (First two letters of functional block)(signal)(state) (reference)(state) for outputs ...

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... DLL bypass mode to 0.4 × Min Max Unit — -0.1 ns 1.4 — 1.5 — -3.2 — ns -2.3 -3.2 — ns -2.3 — 0.2 ns 1.5 — 0.2 ns 1.5 for outputs. For example, t LBIXKH1 clock reference (K) goes LBK clock reference ( LBK of the signal DD Freescale Semiconductor Notes ...

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... Output Signals: LA[27:31]/LBCTL/LBCKE/LOE/ LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] LALE Figure 17. Local Bus Signals, Nonspecial Signals Only (DLL Enabled) MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor = 50 Ω Figure 16. Local Bus AC Test Load t LBIVKH1 t LBIVKH2 ...

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... Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] LALE Figure 18. Local Bus Signals (DLL Bypass Mode) MPC8560 Integrated Processor Hardware Specifications, Rev LBKHKT t LBIVKH1 t LBIVKH2 t LBKLOV1 t LBKLOX1 t LBKLOV2 t t LBKLOX2 LBKLOV3 t t LBKLOV4 LBOTOT t LBIXKH1 t LBIXKH2 t LBKLOZ1 t LBKLOZ2 Freescale Semiconductor ...

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... GPCM Mode Output Signals: LCS[0:7]/LWE UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 19. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Enabled) MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor t LBKHOZ1 t LBKHOV1 t LBIVKH2 t LBIVKH1 t ...

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... Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 20. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass Mode) MPC8560 Integrated Processor Hardware Specifications, Rev LBKHKT t t LBKLOX1 LBKLOV1 t LBIVKH2 t LBIVKH1 t LBKLOZ1 t LBIXKH2 t LBIXKH1 Freescale Semiconductor ...

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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 21. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Enabled) MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor t LBKHOZ1 t LBKHOV1 t LBIVKH2 t LBIVKH1 ...

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... Output high voltage (I = –8.0 mA) OH Output low voltage (I = 8.0 mA) OL MPC8560 Integrated Processor Hardware Specifications, Rev LBKHKT t LBKLOV1 Table 33. CPM DC Electrical Characteristics Symbol Min V 2 GND — LBKLOX1 t LBIVKH2 t LBIXKH2 t LBIVKH1 t LBIXKH1 Max Unit Notes 3.465 — 0 Freescale Semiconductor t LBKLOZ1 ...

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... CPM internal clock. PIO/TIMER outputs should be treated as asynchronous. Table 35. CPM Output AC Timing Specifications Characteristic FCC outputs—internal clock (NMSI) delay FCC outputs—external clock (NMSI) delay MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Symbol Min Max V 2.4 — ...

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... Z 0 Figure 23. CPM AC Test Load Table 34 t FIIXKH t FIIVKH t FIKHOX (continued)1 2 Min Max 0.5 10 NIKHOX 2 8 NEKHOX 2 11 SEKHOX 2.5 11 TDKHOX symbolizes the FCC inputs FIKHOX Ω and Table 35. Note that although the t FIKHOX Freescale Semiconductor Unit for ...

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... Input Signals: SCC/SPI (See Note) Output Signals: SCC (See Note) Output Signals: SPI (See Note) Note: The clock edge is selectable on SCC and SPI. Figure 27. SCC/SPI AC Timing External Clock Diagram MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor t FEIXKH t FEIVKH t FEKHOX t FEKHOX t FCCH t ...

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... BRGCLK/16512 SCL t 1/(2 SDHDL t 1/(2 SCLCH t 1/(2 SCHCL t 2/(divider * f SCHDL t 3/(divider * f SDLCL t 2/(divider * f SCLDX t 3/(divider * f SDVCH Max Unit 1 F MAX BRGCLK/48 ) — SCL ) — SCL ) — SCL ) — SCL ) — SCL ) — SCL ) — SCL Freescale Semiconductor ...

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... Bus free time between transmissions Low period of SCL High period of SCL 2 Start condition setup time 2 Start condition hold time 2 Data hold time 2 Data setup time MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor 2 Table 36. CPM Timing (continued) Symbol Min t — SRISE t — SFALL ...

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... SCHCL t 420 SCHDL t 630 SDLCL t 420 SCLDX t 630 SDVCH t — SRISE t — SFALL t 420 SCHDH Max Unit μs 1 303 ns μs — Max Unit 400 KHz 400 KHz μs — μs — μs — — ns — ns — ns — ns 250 — ns Freescale Semiconductor ...

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... R (rise (fall). 3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4. Non-JTAG signal input timing with respect Non-JTAG signal output timing with respect Guaranteed by design. MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Table 2). 2 Symbol f ...

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... MPC8560 Integrated Processor Hardware Specifications, Rev Ω JTKHKL t JTG VM = Midpoint Voltage ( TRST VM = Midpoint Voltage (OV DD /2) Figure 33. TRST Timing Diagram VM t JTDVKH t JTKLDV t JTKLDZ VM = Midpoint Voltage (OV DD /2) Figure 34. Boundary-Scan Timing Diagram Ω JTGR t JTGF JTDXKH Input Data Valid Output Data Valid Freescale Semiconductor ...

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... Output voltage (open drain or open collector) condition = 3 mA sink current. 2. Refer to the MPC8560 PowerQUICC III Integrated Communications Processor Preliminary Reference Manual for information on the digital filter used. 3. I/O pins will obstruct the SDA and SCL lines if OV MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor VM t JTIVKH t ...

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... For example symbolizes I C timing (I2) for the time that clock reference (K) going to the low I2C of the SCL signal) to bridge IHmin ) of the SCL signal. I2CL Ω Freescale Semiconductor Unit kHz μs μs μs μs ns μs μs μ I2DVKH I2C ...

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... This section describes the general AC timing parameters of the PCI/PCI-X bus of the MPC8560. Note that the SYSCLK signal is used as the PCI input clock. 66 MHz. Table 43. PCI AC Timing Specifications at 66 MHz Parameter SYSCLK to output valid Output hold from SYSCLK MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor t t I2DVKH I2KHKL t I2SXKL t ...

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... Also, t SYS is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local Min Max Unit Notes — 3.0 — — — clocks SYS — clocks (first two letters of functional for outputs. For PCRHFV Freescale Semiconductor ...

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... SYSCLK to output high impedance Input setup time to SYSCLK Input hold time from SYSCLK REQ64 to HRESET setup time HRESET to REQ64 hold time HRESET high to first FRAME assertion MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor = 50 Ω Figure 38. PCI/PCI-X AC Test Load t PCIVKH CLK ...

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... PCKHOV CYC Symbol Min Max t — 3.8 PCKHOV t 0.7 — PCKHOX t — 7 PCKHOZ t 1.4 — PCIVKH t 0.5 — PCIXKH t 10 — PCRVRH PCRHRX t 10 — PCRHFV t 10 — PCIVRH Unit Notes clocks PCRHFV Unit Notes clocks clocks 10, 12 clocks 12 Freescale Semiconductor ...

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... Output low common mode voltage Common mode offset voltage Differential termination Short circuit current (either output) MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Symbol t PCRHIX is a minimum of 1.4 ns rather than the minimum of 1 the PCI-X 1. minimum of 10 clocks rather than the minimum of 5 clocks in the PCI-X 1.0a of 3.3 V ± ...

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... V ± 5%. DD Symbol | See Figure 41(b). OLD . OHD . OLD = |V – See Figure 41(c). OHCM OLCM Symbol IHD V ILD V ICM R IN Min Max Unit — Min Max Unit 0 2.4 V 100 600 mV –600 –100 mV 0.050 2.350 V 90 110 W Freescale Semiconductor Notes 8 Notes — — ...

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... The differential output signal of the transmitter, V • The differential input signal of the receiver, V • The differential output signal of the transmitter or input signal of the receiver, ranges from A – B volts to – (A – B) volts. MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor TERM 100 Ω (no m) ...

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... With the transmit output (or receiver input) eye diagram, the user can determine if the transmitter output (or receiver input) is compliant with an oscilloscope with the appropriate software. MPC8560 Integrated Processor Hardware Specifications, Rev Freescale Semiconductor ...

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... Data specifications apply only to data signals (FRAME, D[0:7]). Table 48. RapidIO Driver AC Timing Specifications—500 Mbps Data Rate Characteristic Differential output high voltage Differential output low voltage MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor 1–X2 Time (UI) Figure 43. Example Compliance Mask ...

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... RISE DV 1260 — t — 180 DPAIR t –180 180 SKEW,PAIR Figure 44. Range Symbol Min Max V 200 540 OHD V –540 –200 OLD 133 — FALL t 133 — RISE DV 800 — t — 133 DPAIR t –133 133 SKEW,PAIR Figure 44. Unit Notes % Unit Notes Freescale Semiconductor ...

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... V OHDmax V OHDmin 0 V OLDmax V OLDmin MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Symbol V OHD V OLD DC t FALL t RISE DV ...

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... If skew was present, the eye pattern would be shifted to the left or right relative to the oscilloscope trigger point – Oscilloscope (Recording) Trigger Point Figure 45. Example Driver Output Eye Pattern MPC8560 Integrated Processor Hardware Specifications, Rev 1.0 UI 1.0 UI Eye Used for Compliance Eye Pattern Testing Freescale Semiconductor ...

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... Measured Measured using the RapidIO receive mask shown in 3. See Figure 49. 4. See Figure 48 and Figure 49. 5. Guaranteed by design. MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Table 51. A receiver shall comply with the Range Symbol Min Max 1080 t — DPAIR t – ...

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... MPC8560 Integrated Processor Hardware Specifications, Rev Symbol Min 425 t — DPAIR t –200 SKEW,PAIR Figure 46. )/2. The ±100 mV minimum data valid and min DV X2 1–X2 Time (UI) Figure 46. RapidIO Receive Mask Range Unit Notes Max — 300 ps 3 200 ps 4 Figure 46. The 1 Freescale Semiconductor ...

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... If skew was present, the eye pattern would be shifted to the left or right relative to the oscilloscope trigger point. 0 – Oscilloscope (Recording) Trigger Point Figure 47. Example Receiver Input Eye Pattern MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor 1.0 UI 1.0 UI Eye Used for Compliance Eye Pattern Testing RapidIO 67 ...

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... CLK0 (CLK1) t SKEW,PAIR Figure 49. Static Skew Diagram and the data valid SKEW,PAIR represents 0 HDmim V HDmim and how the skew DPAIR Center point of the data valid window of the latest allowed data bit for data grouped late with respect to clock t DPAIR Freescale Semiconductor for OD ...

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... Die size Package outline Interconnects Pitch Minimum module height Maximum module height Solder Balls Ball diameter (typical) MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor 12.2 mm × 9 × 783 1 mm 3. Sn/36 Pb/2 Ag 0.5 mm Package and Pin Listings ...

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... MPC8560, 783 FC-PBGA package. Figure 50. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8560 FC-PBGA 1. All dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to datum A. MPC8560 Integrated Processor Hardware Specifications, Rev NOTES Freescale Semiconductor ...

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... PCI_IRDY PCI_STOP PCI_DEVSEL PCI_IDSEL PCI_REQ64 PCI_ACK64 PCI_PERR PCI_SERR PCI_REQ0 PCI_REQ[1:4] PCI_GNT[0] PCI_GNT[1:4] MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Table 54. MPC8560 Pinout Listing Package Pin Number PCI/PCI-X AH12, V13, Y13, AB13, AC13 AA11 Y14 AC10 AG10 AD10 V11 AH10 AA9 ...

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... N23, N24, N25, N26 V21 V20 U23 U27, U28, V18 Y27, Y28, W27, W28, R27 R28 Power Pin Type Notes Supply I/O GV — DD I/O GV — — DD I/O GV — — — — — — — — — — — I/O OV — — — I Freescale Semiconductor ...

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... UDE IRQ[0:7] AA18, Y18, AB18, AG24, AA21, Y19, AA19, AG25 IRQ8 IRQ9/DMA_DREQ3 IRQ10/DMA_DACK3 IRQ11/DMA_DDONE3 IRQ_OUT EC_MDC EC_MDIO MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Package Pin Number P27 P28 AA27, AA28, T26, P21 U19 U22 V28 V27 V23 V22 T27 ...

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... C10 D9 F8 F9, E9, C9, B9, A9, H9, G10, F10 H8 A8 E10 RapidIO Interface Y25 Y24 Power Pin Type Notes Supply I LV — — — — — — — — — — — — — — — — — — — — DD Freescale Semiconductor ...

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... RIO_TX_CLK_IN IIC_SDA IIC_SCL HRESET HRESET_REQ SRESET CKSTP_IN CKSTP_OUT TRIG_IN TRIG_OUT/READY MSRCID[0:1] MSRCID[2:4] MDVAL SYSCLK RTC CLK_OUT MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Package Pin Number AE27 AE26 AC20 AE21 AE24 AE25 AF24 AF25 interface AH22 AH23 System Control AH16 ...

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... Notes Supply I OV — — — Power for e500 PLL AV 1 — DD (1.2 V) Power for CCB PLL AV 2 — DD (1.2 V) Power for CPM PLL AV 3 — DD (1.2 V) — — — Power for DDR GV — DD DRAM I/O Voltage (2.5 V) Freescale Semiconductor ...

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... P9, P8, P7, P6, P5, P4, P3, P2, P1, R1, R2, R3, R4, R5, PC[0:31] R8, R9, R10, R11, T9, T6, T5, T4, T1, U1, U2, U3, U4, U7, U8, U9, U10, V9, V6, V5, V4, V3, V2, V1, W1, W2, MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Package Pin Number A4, C5, E7, H10 N27 AH26, AH27, AH28, AG28, AF28, AE28, ...

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... MPC8560 Integrated Processor Hardware Specifications, Rev Package Pin Number AC1, AD1, AD2, AD5, AD6, AE3, AE2 . DD Ratio.” Ratio.” /GND planes internally and may be used by the core power supply to improve tracking Power Pin Type Supply I when using DD Freescale Semiconductor Notes — ...

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... The memory bus speed is half of the DDR data rate, hence, half of the platform clock frequency. 3.)The 1.0 GHz core frequency is based on a 1.3 V VDD supply voltage. MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Maximum Processor Core Frequency 667 MHz 833 MHz ...

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... CCB clock: SYSCLK (PCI bus) 10:1 ratio CCB clock: SYSCLK (PCI bus) Reserved 12:1 ratio CCB clock: SYSCLK (PCI bus) Reserved Reserved Reserved Table 58. e500 Core to CCB Ratio Ratio Description 00 2:1 e500 core:CCB 01 5:2 e500 core:CCB 10 3:1 e500 core:CCB 11 7:2 e500 core:CCB Table 58. Freescale Semiconductor ...

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... Junction-to-ambient Natural Convection on four layer board (2s2p) Junction-to-ambient (@100 ft/min or 0.5 m/s) on four layer board (2s2p) Junction-to-ambient (@200 ft/min or 1 m/s) on four layer board (2s2p) Junction-to-board thermal MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor SYSCLK (MHz) 33.33 41.63 66.67 Platform/CCB Frequency (MHz) ...

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... Concord, NH 03301 Internet: www.aavidthermalloy.com MPC8560 Integrated Processor Hardware Specifications, Rev Figure 51. The heat sink should be attached to the printed-circuit FC-PBGA Package Heat Sink Heat Sink Clip Adhesive or Lid Die Printed-Circuit Board 603-224-9988 Symbol Value Unit Notes R 0.8 •C/W C/W 4 θJC Freescale Semiconductor ...

Page 83

... W/m•K. The nickel plated copper lid is modeled as 12x14x1 mm. Note that the die and lid are not centered on the substrate; there is a 1.5 mm offset documented in the case outline drawing in Figure 50. MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor 408-749-7601 818-842-7277 408-436-8770 800-522-6752 ...

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... Side View of Model (Not to Scale 0.6 0.6 1.9 y Top View of Model (Not to Scale) 1.6 Figure 52. MPC8560 Thermal Model Table 60, the intrinsic internal conduction thermal resistance paths Adhesive Lid Bump/underfill Die Substrate and solder balls Substrate Heat Source Freescale Semiconductor ...

Page 85

... Heating the heat sink to 40-50 interface material and make the removal easier. The use of an adhesive for heat sink attach is not recommended. MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Radiation Convection Heat Sink Thermal Interface Material ...

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... Internet: www.microsi.com The Bergquist Company th 18930 West 78 St. Chanhassen, MN 55317 Internet: www.bergquistcompany.com MPC8560 Integrated Processor Hardware Specifications, Rev Silicone Sheet (0.006 in.) Bare Joint Floroether Oil Sheet (0.007 in.) Graphite/Oil Sheet (0.005 in.) Synthetic Grease Contact Pressure (psi) 781-935-4850 800-248-2481 888-642-7674 800-347-4572 Freescale Semiconductor ...

Page 87

... Assuming an air velocity of 2 m/s, we have an effective θ (0.8 C/W +1.0 C/W + 3.3 C/W) × 7 resulting in a die-junction temperature of approximately 71 C which is well within the maximum operating temperature of the component. MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor 888-246-9050 + θ + θ ) × INT ...

Page 88

... For applications with significant vibration requirements, silicone damping material can be applied between the heat sink and plastic frame. MPC8560 Integrated Processor Hardware Specifications, Rev Thermalloy #2328B Pin-fin Heat Sink (25 × 28 × 15 mm) 0.5 1 1.5 2 Approach Air Velocity (m/s) 2.5 3 3.5 Table 60 includes the thermal interface Freescale Semiconductor ...

Page 89

... Figure 56 and Figure 57 Figure 56. Exploded Views ( Heat Sink Attachment using a Plastic Force MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor provide exploded views of the plastic fence, heat sink, and spring clip. Thermal 89 ...

Page 90

... Due to the complexity and the many variations of system-level boundary conditions for today’s microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation convection and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the boards, as well as, system-level designs. MPC8560 Integrated Processor Hardware Specifications, Rev Freescale Semiconductor ...

Page 91

... It should be possible to route directly from the capacitors to the AV pin, which is on the periphery of the 783 FC-PBGA footprint, without the inductance of vias. MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Section 15.2, “Platform/System PLL Ratio.” Section 15.3, “e500 Core PLL Ratio.” ...

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... GND Figure 58. PLL Power Supply Filter Circuit , and LV planes, to enable quick recharging of the smaller chip for all buses except RapidIO, and a AV (or L2AV ) and LV pins of the device required. Unused active high and GND pins (see Figure DD Freescale Semiconductor , and DD DD 59). The ...

Page 93

... DD Local Bus, Ethernet, DUART, Control, Impedance Configuration, Power Management R 43 Target Target P Differential Note: Nominal supply voltages. See MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor is trimmed until the voltage at the pad equals P )/ Pad Data R P OGND Figure 59. Driver Impedance Measurement × ...

Page 94

... LSSD_MODE. These signals are for factory use only and must be pulled up to OVDD for normal machine operation. See the PCI 2.2 specification for all pull-ups required for PCI. MPC8560 Integrated Processor Hardware Specifications, Rev open drain type pins should be pulled up with ~1 kΩ resistors. Freescale Semiconductor ...

Page 95

... IC). Regardless of the numbering, the signal placement recommended in all known emulators. MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor allows the COP port to independently assert HRESET or TRST, Figure 60, for connection to the target system, and is ...

Page 96

... This will prevent TCK from changing state and DD reading incorrect data into the device. • No connection is required for TDI, TMS, or TDO. MPC8560 Integrated Processor Hardware Specifications, Rev COP_TDO COP_TDI 3 4 COP_TRST COP_VDD_SENSE COP_TCK 7 8 COP_CHKSTP_IN COP_TMS KEY 13 No pin GND 15 16 Figure 60. COP Connector Physical Pinout Freescale Semiconductor ...

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... This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed. 6. Asserting SRESET causes a machine check interrupt to the e500 core. MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor COP_HRESET COP_SRESET 5 COP_TRST 10 Ω ...

Page 98

... Listings,” for more information on available package types Platform Revision Level 3, 4 Frequency L = 333 MHz B = Rev. 2.0 J= 266 MHz (SVR = 0x80700020 Rev. 2.1 (SVR = 0x80700021 Rev. 2.1.1 (SVR = 0x80700021 333 MHz B = Rev. 2.0 (SVR = 0x80700020 Rev. 2.1 (SVR = 0x80700021 Rev. 2.1.1 (SVR = 0x80700021) Freescale Semiconductor ...

Page 99

... Updated Section 2.1.2, “Power Sequencing.” 3.4 — • Updated MV REF • Updated MV REF • Added new revision level information to MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Figure 62. MPCnnnntppfffcr MPC85nn xPXxxxn ATWLYYWWA MMMMM ATWLYYWWA MMMMM CCCCC CCCCC YWWLAZ FC-PBGA Table 63 ...

Page 100

... MDC MDKHDV MDKHDX parameter in Table 31 and LBKHOV3 62. Table 27. in Table 31 and Table LBKHOV3 Specifications”. 22, Table 23, and Table 24. 23, Table 24, Table 25, Table 26, and Specifications”. Specifications”. and Figure 25. Materials”. Table 29. Table 32, and updated Figure 17. Table 54. Freescale Semiconductor 32. Table 27. ...

Page 101

... Section 14.1— Changed minimum height from 2.22 to 3.07 and maximum from 2.76 to 3.75 • Section 16.2.4.1—Changed • Section 17.7—Added paragraph that begins “TSEC1_TXD[3:0]...” MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Substantive Change(s) power table ...

Page 102

... DISKEW MCKSKEW2 20—Modified “conditions” for I IH Figure 19—Changed LSYNC_IN to Internal clock at top of each figure t , and t FIIVKH, NIIVKH TDIVKH t t FEKHOX, NIKHOX, NEKHOX, LBKHOX3 ; Addition of SYSCLK and addition of t and t . PIIVKH PIIXKH t ; addition of t TDKHOX PIKHOX. Corrected pin assignments Freescale Semiconductor ...

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... Table 63. Document Revision History (continued) Rev. Date Number 1 — Initial public release MPC8560 Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Substantive Change(s) Document Revision History 103 ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...