MPC8349VVALFB Freescale Semiconductor, MPC8349VVALFB Datasheet - Page 68

• Manufacturer Part Number: MPC8349VVALFB
• Description: IC MPU POWERQUICC II 672-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8349VVALFB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 667MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 672-TBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8349E-MITXE
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.3V
• Operating Supply Voltage (max): 1.36V
• Operating Supply Voltage (min): 1.24V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: TBGA
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 667MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 672
• Rohs Compliant: Yes
• For Use With: MPC8349E-MITX-GP - KIT REFERENCE PLATFORM MPC8349EMPC8349E-MITXE - BOARD REFERENCE FOR MPC8349MPC8349EA-MDS-PB - KIT MODULAR DEV SYSTEM MPC8349E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
3
4
Clocking
Table 57
conditions (see
All frequency combinations shown in the table below may not be available. Maximum operating
frequencies depend on the part ordered, see
Document,”
distributor for more information.
19.1
The system PLL is controlled by the RCWL[SPMF] parameter.
encodings for the system PLL.
68
e300 core frequency (core_clk)
Coherent system bus frequency (csb_clk)
DDR1 memory bus frequency (MCK)
DDR2 memory bus frequency (MCK)
Local bus frequency (LCLKn)
PCI input frequency (CLKIN or PCI_CLK)
Security core maximum internal operating frequency
USB_DR, USB_MPH maximum internal operating frequency
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCK,
LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value of
SCCR[ENCCM], SCCR[USBDRCM] and SCCR[USBMPHCM] must be programmed so that the maximum internal operating
frequency of the security core and USB modules does not exceed the respective values listed in this table.
The DDR data rate is 2x the DDR memory bus frequency.
The DDR data rate is 2x the DDR memory bus frequency.
The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x the
csb_clk frequency (depending on RCWL[LBIUCM]).
provides the operating frequencies for the MPC8349EA TBGA under recommended operating
System PLL Configuration
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
for part ordering details and contact your Freescale Sales Representative or authorized
Table
2).
Characteristic
4
2
3
Table 58. System PLL Multiplication Factors
RCWL[SPMF]
Table 57. Operating Frequencies for TBGA
1
0000
0001
0010
0011
0100
0101
0110
Section 22.1, “Part Numbers Fully Addressed by This
System PLL Multiplication Factor
Reserved
× 16
× 2
× 3
× 4
× 5
× 6
16.67–133
400 MHz
266–400
100–266
100–133
100–133
25–66
133
133
Table 58
16.67–133
533 MHz
266–533
100–333
100–133
100–133
shows the multiplication factor
25–66
133
133
100–166.67
Freescale Semiconductor
16.67–133
667 MHz
266–667
100–333
100–200
25–66
166
166
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit