MPC859TVR133A Freescale Semiconductor, MPC859TVR133A Datasheet - Page 55

• Manufacturer Part Number: MPC859TVR133A
• Description: IC MPU POWERQUICC 133MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC859TVR133A

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 133MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 133 MHz
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 133MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
1
2
3
4
Num
78A
80A
83a
The ratio SyncCLK/L1RCLK must be greater than 2.5/1.
These specs are valid for IDL mode only.
Where P = 1/CLKOUT. Thus, for a 25-MHz CLKO1 rate, P = 40 ns.
These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever is later.
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
L1CLK edge to L1RSYNC, L1TSYNC, invalid
(SYNC hold time)
L1RSYNC, L1TSYNC rise/fall time
L1RXD valid to L1CLK edge (L1RXD setup time)
L1CLK edge to L1RXD invalid (L1RXD hold time)
L1CLK edge to L1ST(1–4) valid
L1SYNC valid to L1ST(1–4) valid
L1CLK edge to L1ST(1–4) invalid
L1CLK edge to L1TXD valid
L1TSYNC valid to L1TXD valid
L1CLK edge to L1TXD high impedance
L1RCLK, L1TCLK frequency (DSC =1)
L1RCLK, L1TCLK width low (DSC =1)
L1RCLK, L1TCLK width high (DSC = 1)
L1CLK edge to L1CLKO valid (DSC = 1)
L1RQ valid before falling edge of L1TSYNC
L1GR setup time
L1GR hold time
L1CLK edge to L1SYNC valid (FSD = 00) CNT =
0000, BYT = 0, DSC = 0)
2
Characteristic
MPC866/MPC859 Hardware Specifications, Rev. 2
Table 21. SI Timing (continued)
4
4
3
4
P + 10
P + 10
35.00
17.00
13.00
10.00
10.00
10.00
10.00
10.00
42.00
42.00
1.00
0.00
Min
—
—
—
—
All Frequencies
16.00 or SYNCCLK/2
CPM Electrical Characteristics
15.00
45.00
45.00
45.00
55.00
55.00
42.00
30.00
Max
0.00
—
—
—
—
—
—
—
—
L1TCLK
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55