MPC855TCVR50D4 Freescale Semiconductor, MPC855TCVR50D4 Datasheet - Page 6

IC MPU POWERQUICC 50MHZ 357PBGA

MPC855TCVR50D4

Manufacturer Part Number
MPC855TCVR50D4
Description
IC MPU POWERQUICC 50MHZ 357PBGA
Manufacturer
Freescale Semiconductor

Specifications of MPC855TCVR50D4

Processor Type
MPC8xx PowerQUICC 32-Bit
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Processor Series
MPC8xx
Core
MPC8xx
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Operating Supply Voltage
2.5 V, 3.3 V
Maximum Operating Temperature
+ 95 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Family Name
MPC8xx
Device Core
PowerQUICC
Device Core Size
32b
Frequency (max)
50MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.465/3.6V
Operating Supply Voltage (min)
2/3.135V
Operating Temp Range
-40C to 95C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC855TCVR50D4
Manufacturer:
FREESCAL
Quantity:
246
Part Number:
MPC855TCVR50D4
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC855TCVR50D4R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
MPC855T Key Features
6
— QMC multichannel features
— Two SMCs (serial management channels)
— One SPI (serial peripheral interface)
— One I
— Time slot assigner (TSA) supporting TDMa only
— Parallel interface port
— Low power support
— Debug interface
– Up to 32 independent communication channels on a single SCC
– Arbitrary mapping of 0–31 channels to any of 0–31 TDM time slots
– Supports either transparent or HDLC protocols for each channel
– Independent transmit and receive buffer descriptors and event/interrupt reporting for each
– UART
– Transparent
– General circuit interface (GCI) controller
– May be connected to the time-division-multiplexed (TDM) channels
– Supports master and slave modes
– Supports multimaster operation on the same bus
– Supports master and slave modes
– Multimaster environment support
– Allows SCC and SMCs to run in multiplexed and/or nonmultiplexed operation
– Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined
– 1- or 8-bit resolution
– Allows independent transmit and receive routing, frame syncs, clocking
– Allows dynamic changes
– May be internally connected to three serial channels (one SCC and two SMCs)
– Centronics™ interface support
– Supports fast connection between compatible ports on MPC860 or MC68360
– Full-on–all units fully powered
– Doze–core functional units disabled except time base, decrementer, PLL, memory
– Sleep–all units disabled except RTC and PIT, PLL active for fast wake-up
– Deep sleep–all units disabled including PLL except RTC and PIT
– Low-power STOP mode provides lowest power dissipation
– Eight comparators: four operate on instruction address, two operate on data address, and
– Supports conditions: =
– Each watchpoint can generate a breakpoint internally
channel
controller, RTC, and CPM in low-power standby
two operate on data
2
C (inter-integrated circuit) port
MPC855T Communications Controller Technical Summary
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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