MPC5200CVR400B Freescale Semiconductor, MPC5200CVR400B Datasheet - Page 18

IC MPU 32BIT 400MHZ 272-PBGA

MPC5200CVR400B

Manufacturer Part Number
MPC5200CVR400B
Description
IC MPU 32BIT 400MHZ 272-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC5200CVR400B

Processor Type
MPC52xx PowerPC 32-Bit
Speed
400MHz
Voltage
1.5V
Mounting Type
Surface Mount
Package / Case
272-PBGA
Processor Series
MPC52xx
Core
e300
Development Tools By Supplier
MEDIA5200KIT1E
Maximum Clock Frequency
400 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
I/o Voltage
2.5 V, 3.3 V
Minimum Operating Temperature
- 40 C
Core Size
32 Bit
No. Of I/o's
56
Ram Memory Size
16KB
Cpu Speed
400MHz
No. Of Timers
8
Embedded Interface Type
CAN, I2C, SCI, SPI
No. Of Pwm Channels
8
Digital Ic Case Style
TEPBGA
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC5200CVR400B
Manufacturer:
Marvell
Quantity:
1 001
Part Number:
MPC5200CVR400B
Manufacturer:
FREESCAL
Quantity:
200
Part Number:
MPC5200CVR400B
Manufacturer:
FREESCALE
Quantity:
365
Part Number:
MPC5200CVR400B
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC5200CVR400B
Manufacturer:
FREESCALE
Quantity:
365
Part Number:
MPC5200CVR400B
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MPC5200CVR400B
0
Part Number:
MPC5200CVR400BM62C
Manufacturer:
FRRESCAL..
Quantity:
2 831
1.3.6.2
In Standard SDRAM, all signals are activated on the MEM_CLK from the Memory Controller and captured on the MEM_CLK
clock at the memory device.
18
data
t
data
DM
DM
mem_clk
MBA (Bank Selects)
Sym
t
t
valid
hold
DQM (Data Mask)
valid
hold
valid
hold
Control Signals
MA (Address)
NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
MDQ (Data)
MEM_CLK
Memory Interface Timing-Standard SDRAM Write Command
Control Signals, Address and MBA Hold after
DQM valid after rising edge of MEM_CLK
MDQ valid after rising edge of MEM_CLK
MDQ hold after rising edge of MEM_CLK
Control Signals, Address and MBA Valid
DQM hold after rising edge of Mem_clk
Figure 5. Timing Diagram—Standard SDRAM Memory Read Timing
after rising edge of MEM_CLK
rising edge of MEM_CLK
MEM_CLK period
t
t
t
valid
valid
Description
valid
Table 19. Standard SDRAM Write Timing
Active
Row
t
hold
DM
valid
MPC5200B Data Sheet, Rev. 4
t
t
hold
hold
NOP
Column
READ
t
t
mem_clk
mem_clk
t
mem_clk
DM
data
Min
× 0.25 – 0.7
× 0.75 – 0.7
7.5
NOP
hold
× 0.5
setup
NOP
t
t
t
mem_clk
mem_clk
mem_clk
data
NOP
Max
× 0.25 + 0.4
× 0.75 + 0.4
× 0.5 + 0.4
hold
NOP
Freescale Semiconductor
Units
ns
ns
ns
ns
ns
ns
ns
NOP
SpecID
A5.10
A5.11
A5.12
A5.13
A5.14
A5.8
A5.9

Related parts for MPC5200CVR400B