MPC5200CVR400B Freescale Semiconductor, MPC5200CVR400B Datasheet - Page 12

IC MPU 32BIT 400MHZ 272-PBGA

MPC5200CVR400B

Manufacturer Part Number
MPC5200CVR400B
Description
IC MPU 32BIT 400MHZ 272-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC5200CVR400B

Processor Type
MPC52xx PowerPC 32-Bit
Speed
400MHz
Voltage
1.5V
Mounting Type
Surface Mount
Package / Case
272-PBGA
Processor Series
MPC52xx
Core
e300
Development Tools By Supplier
MEDIA5200KIT1E
Maximum Clock Frequency
400 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
I/o Voltage
2.5 V, 3.3 V
Minimum Operating Temperature
- 40 C
Core Size
32 Bit
No. Of I/o's
56
Ram Memory Size
16KB
Cpu Speed
400MHz
No. Of Timers
8
Embedded Interface Type
CAN, I2C, SCI, SPI
No. Of Pwm Channels
8
Digital Ic Case Style
TEPBGA
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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1.3
Hyperlinks to the indicated timing specification sections are provided below.
1.3.1
Unless otherwise noted, all test conditions are as follows:
12
1
2
3
The XLB_CLK frequency and e300 PLL Configuration bits must be chosen such that the resulting system
frequencies, CPU (core) frequency, and e300 PLL (VCO) frequency do not exceed their respective maximum or
minimum operating frequencies in
This represents total input jitter—short term and long term combined—and is guaranteed by design. Two different
types of jitter can exist on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected.
Systemic jitter is passed into and through the PLL to the internal clock circuitry.
Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required
for the PLL lock after a stable VDD and CORE_SYSCLK are reached during the power-on reset sequence. This
specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
TA = –40 to 85
Tj = –40 to 115
VDD_CORE = 1.42 to 1.58 V
VDD_IO = 3.0 to 3.6 V
e300 input clock frequency
e300 input clock cycle time
AC Electrical Characteristics
e300 VCO frequency
e300 input clock jitter
e300 PLL relock time
AC Operating Frequency Data
Clock AC Specifications
Resets
External Interrupts
SDRAM
PCI
Local Plus Bus
ATA
Ethernet
AC Test Timing Conditions:
e300 cycle time
e300 frequency
Characteristic
o
o
C
C
Table
Table 11. e300 PLL Specifications
f
t
f
XLB_CLK
XLB_CLK
VCOcore
Sym
f
t
t
t
core
core
jitter
lock
12.
MPC5200B Data Sheet, Rev. 4
Notes
(1)
(2)
(3)
(1)
(1)
2.85
2.73
Min
400
50
25
USB
SPI
MSCAN
I
J1850
PSC
GPIOs and Timers
IEEE 1149.1 (JTAG) AC Specifications
2
C
Typical
1200
Max
40.0
50.0
550
367
150
100
Freescale Semiconductor
MHz
MHz
MHz
Unit
ns
ns
ps
μs
SpecID
O4.1
O4.2
O4.3
O4.4
O4.5
O4.6
O4.7

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