MPC8241LZQ200D Freescale Semiconductor, MPC8241LZQ200D Datasheet - Page 8

• Manufacturer Part Number: MPC8241LZQ200D
• Description: IC MPU 32BIT 200MHZ PPC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8241LZQ200D

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 200MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: MPC82XX
• Device Core: PowerQUICC II
• Device Core Size: 32b
• Frequency (max): 200MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

Electrical and Thermal Characteristics
Figure 2
8
Notes:
1. Numbers associated with waveform separations correspond to caution numbers listed in
2. See the Cautions section of
3. Refer to
4. Refer to
5. HRST_CPU/HRST_CTRL must transition from a logic 0 to a logic 1 in less than one SDRAM_SYNC_IN
6. PLL_CFG signals must be driven on reset and must be held for at least 25 clock cycles after the negation
shows supply voltage sequencing and separation cautions.
clock cycle for the device to be in the nonreset state.
of HRST_CTRL and HRST_CPU negate in order to be latched.
3.3 V
5 V
2 V
0
Configuration Pins
Table 8
Table 10
HRST_CPU and
HRST_CTRL
Figure 2. Supply Voltage Sequencing and Separation Cautions
Power Supply Ramp Up
MPC8241 Integrated Processor Hardware Specifications, Rev. 10
for details on PLL relock and reset signal assertion timing requirements.
for details on reset configuration pin setup timing requirements.
3
Reset
6
Table 2
6
V
5
Maximum Rise Time Must be Less Than
DD
for details on this topic.
5
Stable
One External Memory Clock Cycle
2
2
See Note 1
Clock Cycles Setup Time
Nine External Memory
Relock
100 µs
Time
PLL
3
External Memory
HRST_CPU and
Clock Cycles
HRST_CTRL
Asserted 255
LV
GV
V
DD
DD
DD
/AV
@ 5 V
_OV
4
DD
5
DD
/AV
/(LV
3
DD
2
DD
@ 3.3 V - - - -)
PLL
VM = 1.4 V
Table
Freescale Semiconductor
6
Time
2.