CY7C68013-56PVC Cypress Semiconductor Corp, CY7C68013-56PVC Datasheet - Page 12

IC MCU USB PERIPH HI SPD 56SSOP

CY7C68013-56PVC

Manufacturer Part Number
CY7C68013-56PVC
Description
IC MCU USB PERIPH HI SPD 56SSOP
Manufacturer
Cypress Semiconductor Corp
Series
EZ-USB FX2LP™r
Datasheet

Specifications of CY7C68013-56PVC

Applications
USB Microcontroller
Core Processor
8051
Program Memory Type
ROMless
Controller Series
CY7C680xx
Ram Size
16K x 8
Interface
I²C, USB, USART
Number Of I /o
24
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-SSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1332

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Two memory maps are shown in the following diagrams:
Figure 3-1 Internal Code Memory, EA = 0
Figure 3-2 External Code Memory, EA = 1.
3.10.2
This mode implements the internal eight-kbyte block of RAM (starting at 0) as combined code and data memory. When external
RAM or ROM is added, the external read and write strobes are suppressed for memory spaces that exist inside the chip. This
allows the user to connect a 64-kbyte memory without requiring address decodes to keep clear of internal memory spaces.
Only the internal eight kbytes and scratch pad 0.5 kbytes RAM spaces have the following access:
Document #: 38-08012 Rev. *C
• USB download
• USB upload
• Setup data pointer
• I
2
C-compatible interface boot load.
Internal Code Memory, EA = 0
*SUDPTR, USB upload/download, I
FFFF
E200
E1FF
E000
1FFF
0000
Data (RD#,WR#)*
Eight kbytes RAM
Code and Data
(PSEN#,RD#,WR#)*
0.5 kbytes RAM
Figure 3-1. Internal Code Memory, EA = 0
7.5 kbytes
US B regs and
4k EP buffers
(RD#,WR#)
Inside FX2
(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)
(OK to populate
data memory
here—RD#/WR#
strobes are not
active)
2
48 kbytes
External
Data
Memory
(RD#,WR#)
C-compatible interface boot access
Data
Outside FX2
(OK to populate
program
memory here—
PSEN# strobe
is not active)
56 kbytes
External
Code
Memory
(PSEN#)
Code
CY7C68013
Page 12 of 52

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