CY7C63723-PC Cypress Semiconductor Corp, CY7C63723-PC Datasheet - Page 23

• Manufacturer Part Number: CY7C63723-PC
• Description: IC MCU 8K LS USB/PS-2 18-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63723-PC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C637xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 10
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1322

17.5
For SPI, an interrupt request is generated after a byte is
received or transmitted. See Section 21.3 for details on the SPI
interrupt.
17.6
The GPIO pins used for SPI outputs (P0.5–P0.7) contain a
bypass mode, as shown in the GPIO block diagram
(Figure 12-1). Whenever the SPI block is inactive (Mode[5:4]
= 00), the bypass value is 1, which enables normal GPIO
Table 17-1. SPI Pin Assignments
Document #: 38-08022 Rev. *B
Master Out, Slave In (MOSI)
Master In, Slave Out (MISO)
CPHA = 0:
SCK (CPOL = 0)
SCK (CPOL = 1)
SS
MOSI/MISO
Data Capture Strobe
Interrupt Issued
CPHA = 1:
MOSI/MISO
Data Capture Strobe
Interrupt Issued
SPI Interrupt
SPI Modes for GPIO Pins
Slave Select (SS)
SPI Function
SCK
x
MSB
MSB
FOR
FOR
GPIO Pin
P0.4
P0.5
P0.6
P0.7
Figure 17-4. SPI Data Timing
For Master Mode, Firmware sets SS, may use any GPIO pin.
For Slave Mode, SS is an active LOW input.
Data output for master, data input for slave.
Data input for master, data output for slave.
SPI Clock: Output for master, input for slave.
operation. When SPI master or slave modes are activated, the
appropriate bypass signals are driven by the hardware for
outputs, and are held at 1 for inputs. Note that the corre-
sponding data bits in the Port 0 Data Register must be set
to 1 for each pin being used for an SPI output. In addition,
the GPIO modes are not affected by operation of the SPI
block, so each pin must be programmed by firmware to the
desired drive strength mode.
For GPIO pins that are not used for SPI outputs, the SPI
bypass value in Figure 12-1 is always 1, for normal GPIO
operation.
Comment
LSB
LSB
CY7C63722
CY7C63723
CY7C63743
x
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