CY7C63231A-SC Cypress Semiconductor Corp, CY7C63231A-SC Datasheet - Page 4

• Manufacturer Part Number: CY7C63231A-SC
• Description: IC MCU 3K USB LS PERIPH 18-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63231A-SC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (3 kB)
• Controller Series: CY7C632xx
• Ram Size: 96 x 8
• Interface: USB
• Number Of I /o: 10
• Voltage - Supply: 3.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 18-SOIC (7.5mm Width)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: SOIC
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1317

Figure 8-1. Program Memory Space with Interrupt Vector Table ........................................................ 11
Figure 9-1. Clock Oscillator On-chip Circuit ......................................................................................... 14
Figure 9-2. Clock Configuration Register (Address 0xF8) ................................................................... 14
Figure 10-1. Watchdog Reset (WDR, Address 0x26) .......................................................................... 17
Figure 12-1. Block Diagram of GPIO Port (one pin shown) ................................................................. 19
Figure 12-2. Port 0 Data (Address 0x00) ............................................................................................. 19
Figure 12-3. Port 1 Data (Address 0x01) ............................................................................................. 20
Figure 12-4. GPIO Port 0 Mode0 Register (Address 0x0A) ................................................................. 20
Figure 12-5. GPIO Port 0 Mode1 Register (Address 0x0B) ................................................................. 20
Figure 12-6. GPIO Port 1 Mode0 Register (Address 0x0C) ................................................................ 20
Figure 12-7. GPIO Port 1 Mode1 Register (Address 0x0D) ................................................................ 21
Figure 12-8. Port 2 Data Register (Address 0x02) .............................................................................. 22
Figure 13-1. USB Status and Control Register (Address 0x1F) .......................................................... 23
Figure 14-1. USB Device Address Register (Address 0x10) ............................................................... 25
Figure 14-2. Endpoint 0 Mode Register (Address 0x12) ..................................................................... 25
Figure 14-3. USB Endpoint EP1 Mode Registers (Address 0x14) ...................................................... 26
Figure 14-4. Endpoint 0 and 1 Counter Registers (Addresses 0x11 and 0x13) .................................. 27
Figure 16-1. Diagram of USB - PS/2 System Connections ................................................................. 28
Figure 17-1. Timer LSB Register (Address 0x24) ................................................................................ 29
Figure 17-2. Timer MSB Register (Address 0x25) ............................................................................... 29
Figure 17-3. Timer Block Diagram ....................................................................................................... 29
Figure 18-1. Processor Status and Control Register (Address 0xFF) ................................................. 29
Figure 19-1. Global Interrupt Enable Register (Address 0x20) ............................................................ 32
Figure 19-2. Endpoint Interrupt Enable Register (Address 0x21) ........................................................ 33
Figure 19-3. Interrupt Controller Logic Block Diagram ........................................................................ 34
Figure 19-4. Port 0 Interrupt Enable Register (Address 0x04) ............................................................ 34
Figure 19-5. Port 1 Interrupt Enable Register (Address 0x05) ............................................................ 34
Figure 19-6. Port 0 Interrupt Polarity Register (Address 0x06) ............................................................ 35
Figure 19-7. Port 1 Interrupt Polarity Register (Address 0x07) ............................................................ 35
Figure 19-8. GPIO Interrupt Diagram .................................................................................................. 35
Figure 24-1. Clock Timing .................................................................................................................... 45
Figure 24-2. USB Data Signal Timing .................................................................................................. 45
Figure 24-3. Receiver Jitter Tolerance ................................................................................................ 45
Figure 24-4. Differential to EOP Transition Skew and EOP Width ...................................................... 46
Figure 24-5. Differential Data Jitter ...................................................................................................... 46
Table 8-1. I/O Register Summary ........................................................................................................ 13
Table 11-1. Wake-up Timer Adjust Settings ........................................................................................ 18
Table 12-1. Ports 0 and 1 Output Control Truth Table ........................................................................ 21
Table 13-1. Control Modes to Force D+/D– Outputs ........................................................................... 24
Table 19-1. Interrupt Vector Assignments ........................................................................................... 31
Table 20-1. USB Register Mode Encoding for Control and Non-Control Endpoint ............................. 36
Table 20-2. Decode table for Table 20-3: “Details of Modes for Differing Traffic Conditions” ............. 38
Table 20-3. Details of Modes for Differing Traffic Conditions .............................................................. 39
Table 26-1. CY7C63221A-XC Probe Pad Coordinates in microns ((0,0) to bond pad centers) .......... 48
Document #: 38-08028 Rev. *B
FOR
FOR
LIST OF FIGURES
LIST OF TABLES
CY7C63221/31A
enCoRe™ USB
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