CY7C64613-80NC Cypress Semiconductor Corp, CY7C64613-80NC Datasheet - Page 18

• Manufacturer Part Number: CY7C64613-80NC
• Description: IC MCU USB EZ FX 8K RAM 80-PQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX™r

Specifications of CY7C64613-80NC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C646xx
• Ram Size: 8K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1312

3.2
Document #: 38-08005 Rev. **
128
104
101
44
45
46
96
97
98
53
54
70
71
73
74
76
77
50
49
7
5
CY7C646xx Pin Descriptions
80
65
25
26
27
62
57
58
59
4
2
52
42
41
37
38
22
23
20
19
4
2
XCLK
Reserved
Reserved
Reserved
RDY2 or
AOE
RDY3 or
BOE
RDY4 or
SLWR
RDY5 or
SLRD
CTL0 or
AINFLAG
CTL1 or
BINFLAG
CTL2 or
AOUTFLAG
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
WAKEUP#
SCL
Name
Output
Output
Output
Rsrvd
Rsrvd
Rsrvd
Rsrvd
Rsrvd
Rsrvd
Rsrvd
Rsrvd
Rsrvd
Rsrvd
Type
Input
Input
Input
Input
Input
Input
OD
(continued)
Default
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
X
X
X
X
X
X
X
Z
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY2 is a GPIF input signal.
AOE is the output enable input for the A-OUT FIFO.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY3 is a GPIF input signal.
BOE is the output enable input for the B-OUT FIFO.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY4 is a GPIF input signal.
SLWR is the input-only write strobe for the slave FIFOs connected
to AFI[7..0] and/or BFI[7..0].
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY5 is a GPIF input signal.
SLRD is the input-only read strobe for the slave FIFOs connected
to AFI[7..0] and/or BFI[7..0].
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL0 is a GPIF control output.
AINFLAG is the A-IN FIFO flag output which indicates a program-
mable level of FIFO fullness.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL1 is a GPIF control output.
BINFLAG is the B-IN FIFO flag output which indicates a program-
mable level of FIFO fullness.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL2 is a GPIF control output.
AOUTFLAG is the A-OUT FIFO flag output which indicates a pro-
grammable level of FIFO fullness.
External clock input, used for synchronously clocking data into the
slave FIFOs. XCLK also serves as a timing reference for all slave
FIFO control signals and GPIF.
Reserved. Connect to Ground.
Reserved. Connect to Ground.
Reserved. Connect to Ground.
Reserved. Connect to Ground.
Reserved. Connect to Ground.
Reserved. Connect to Ground.
Reserved. Connect to Ground.
Reserved. Connect to Ground.
Reserved. Leave open.
Reserved. Connect to Ground.
USB Wakeup. If the 8051 is in suspend, a HIGH-to-LOW edge on
this pin starts up the oscillator and interrupts the 8051 to allow it to
exit the suspend mode. Holding WAKEUP# LOW inhibits the EZ-
USB chip from suspending.
I
ripheral is attached.
2
C Clock. Connect to V
CC
Description
with a 1K resistor, even if no I
CY7C64601/603/613
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C pe-