CY7C64613-80NC Cypress Semiconductor Corp, CY7C64613-80NC Datasheet - Page 16

• Manufacturer Part Number: CY7C64613-80NC
• Description: IC MCU USB EZ FX 8K RAM 80-PQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX™r

Specifications of CY7C64613-80NC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C646xx
• Ram Size: 8K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1312

3.2
Document #: 38-08005 Rev. **
Port D
128
123
124
125
126
56
57
58
59
60
61
63
CY7C646xx Pin Descriptions
80
73
74
75
76
30
31
32
33
34
35
36
52
48
49
50
51
PC4 or
PC5 or
PC6 or
PC7 or
T0 or
CTL1
T1 or
CTL3
WR# or
CTL4
RD# or
CTL5
PD0 or
GDB[0] or
BFI [0]
PD1 or
GDB[1] or
BFI [1]
PD2 or
GDB[2] or
BFI [2]
PD3 or
GDB[3] or
BFI [3]
PD4 or
GDB[4] or
BFI [4]
PD5 or
GDB[5] or
BFI [5]
PD6 or
GDB[6] or
BFI [6]
Name
Type
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
(continued)
Default
(PC4)
(PC5)
(PC6)
(PC7)
(PD0)
(PD1)
(PD2)
(PD3)
(PD4)
(PD5)
(PD6)
I
I
I
I
I
I
I
I
I
I
I
Multiplexed pin whose function is selected by the PORTCCFG.4
and PORTCGPIF.4 bits.
PC4 is a bidirectional I/O port pin.
T0 is the active-HIGH T0 signal for 8051 Timer0, which provides the
input to Timer0 when C/T0 is 1. When C/T0 is 0, Timer0 does not
use this bit.
CTL1 is a GPIF output signal.
Multiplexed pin whose function is selected by the PORTCCFG.5
and PORTCGPIF.5 bits.
PC5 is a bidirectional I/O port pin.
T1 is the active-HIGH T1 signal for 8051 Timer1, which provides the
input to Timer1 when C/T1 is 1. When C/T1 is 0, Timer1 does not
use this bit.
CTL3 is a GPIF output signal.
Multiplexed pin whose function is selected by the PORTCCFG.6
and PORTCGPIF.6 bits.
PC6 is a bidirectional I/O port pin.
WR# is the active-LOW write strobe output for external memory. If
the WR# signal is used, it should be externally pulled up to V
ensure that the write strobe is inactive at power-on.
CTL4 is a GPIF output signal.
Multiplexed pin whose function is selected by the PORTCCFG.7
and PORTCGPIF.7 bits.
PC7 is a bidirectional I/O port pin.
RD# is the active-LOW read strobe output for external memory. If
the RD# signal is used, it should be externally pulled up to V
ensure that the write strobe is inactive at power-on.
CTL5 is a GPIF output signal.
Port D is multiplexed between three sources:
PD0–PD7 are bidirectional I/O port pins.
GDB[7..0] is the GPIF B data bus.
BFI[7..0] is the bidirectional B-FIFO data bus.
Multiplexed pin whose function is selected by the IFCONFIG[2..0]
bits.
BFI [0] is the bidirectional B-FIFO data bus.
Multiplexed pin whose function is selected by the IFCONFIG[2..0]
bits.
BFI [1] is the bidirectional B-FIFO data bus.
Multiplexed pin whose function is selected by the IFCONFIG[2..0]
bits.
BFI [2] is the bidirectional B-FIFO data bus.
Multiplexed pin whose function is selected by the IFCONFIG[2..0]
bits.
BFI [3] is the bidirectional B-FIFO data bus.
Multiplexed pin whose function is selected by the IFCONFIG[2..0]
bits.
BFI [4] is the bidirectional B-FIFO data bus.
Multiplexed pin whose function is selected by the IFCONFIG[2..0]
bits.
BFI [5] is the bidirectional B-FIFO data bus.
Multiplexed pin whose function is selected by the IFCONFIG[2..0]
bits.
BFI [6] is the bidirectional B-FIFO data bus.
Description
CY7C64601/603/613
Page 16 of 42
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