AN2135SC Cypress Semiconductor Corp, AN2135SC Datasheet - Page 225

• Manufacturer Part Number: AN2135SC
• Description: IC MCU 8051 8K RAM 24MHZ 44QFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB®r

Specifications of AN2135SC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: AN213x
• Ram Size: 8K x 8
• Interface: I²C, USB
• Number Of I /o: 8
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1308

* See Table 12-5 for individual control/status register addresses.
Bit 1:
The BSY bit indicates the status of the endpoint’s IN Buffer INnBUF. The EZ-USB core
sets BSY=0 when the endpoint’s IN buffer is empty and ready for loading by the 8051.
The 8051 sets BSY=1 by loading the endpoint’s byte count register.
When BSY=1, the 8051 should not write data to an IN endpoint buffer, because the end-
point FIFO could be in the act of transferring data to the host over the USB. BSY=0 when
the USB IN transfer is complete and endpoint RAM data is available for 8051 access.
USB IN tokens for the endpoint are NAKd while BSY=0 (the 8051 is still loading data
into the endpoint buffer).
A 1-to-0 transition of BSY (indicating that the 8051 can access the buffer) generates an
interrupt request for the IN endpoint. After the 8051 writes the data to be transferred to
the IN endpoint buffer, it loads the endpoint’s byte count register with the number of bytes
to transfer, which automatically sets BSY=1. This enables the IN transfer of data to the
host in response to the next IN token. Again, the CPU should never load endpoint data
while BSY=1.
The 8051 writes a “1” to an IN endpoint busy bit to disarm a previously armed endpoint.
(This sets BSY=0.) The 8051 program should do this only after a USB bus reset, or when
the host selects a new interface or alternate setting that uses the endpoint. This prevents
stale data from a previous setting from being accepted by the host’s first IN transfer that
uses the new setting.
To disarm a paired IN endpoint, write a “1” to the busy bit for both endpoints in the pair.
Page 12-32
INnCS
Note:
Even though the register description shows bit 1 as “R/W,” the 8051 can only clear this
bit by writing a “1” to it. The 8051 can not directly set this bit.
b7
R
0
-
INnBSY
b6
R
0
-
Endpoint (1-7) IN Control and Status
Figure 12-26. IN Control and Status Registers
b5
R
0
-
IN Endpoint (1-7) Busy
Chapter 12. EZ-USB Registers
b4
R
0
-
b3
R
-
0
b2
R
0
-
INnBSY
R/W
b1
0
7FB6-7FC2*
EZ-USB TRM v1.9
INnSTL
R/W
b0
0