AN2135SC Cypress Semiconductor Corp, AN2135SC Datasheet - Page 168

• Manufacturer Part Number: AN2135SC
• Description: IC MCU 8051 8K RAM 24MHZ 44QFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB®r

Specifications of AN2135SC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: AN213x
• Ram Size: 8K x 8
• Interface: I²C, USB
• Number Of I /o: 8
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1308

Referring to the logic inside the dotted lines, each USB interrupt source has an interrupt
request latch. The EZ-USB core sets an IRQ bit, and the 8051 clears an IRQ bit by writing
a “1” to it. The output of each latch is ANDed with an IEN (Interrupt Enable) bit and then
ORd with all the other USB interrupt request sources.
The EZ-USB core prioritizes the USB interrupts, and constructs an Autovector, which
appears in the AVEC register. The interrupt vector values IV[4..0] are shown to the left of
the interrupt sources (shaded boxes). 00 is the highest priority, 15 is the lowest. If two
USB interrupts occur simultaneously, the prioritization affects which one is first indicated
in the AVEC register. If the 8051 has enabled Autovectoring, the AVEC byte replaces
byte 0x45 in 8051 program memory. This causes the USB interrupt automatically to vec-
tor to different addresses for each USB interrupt source. This mechanism is explained in
detail in Section 9.10, "USB Autovectors."
Due to the OR gate in Figure 9-2, any of the USB interrupt sources sets the 8051 USB
interrupt request latch, whose state appears as an interrupt request in the 8051 SFR bit
EXIF.4. The 8051 enables the USB interrupt by setting SFR bit EIE.0. To clear the USB
interrupt request the 8051 writes a zero to the EXIF.4 bit. Note that this is the opposite of
clearing any of the individual USB interrupt sources, which the 8051 does by writing a “1”
to the IRQ bit.
When a USB resource requires service (for example, a SOF token arrives or an OUT token
arrives on a BULK endpoint), two things happen. First, the corresponding Interrupt
Request Latch is set. Second, a pulse is generated, ORd with the other USB interrupt
logic, and routed to the 8051 INT2 input. The pulse is required because INT2 is edge trig-
gered.
When the 8051 finishes servicing a USB interrupt, it clears the particular IRQ bit by writ-
ing a “1” to it. If any other USB interrupts are pending, the act of clearing the IRQ causes
the EZ-USB core logic to generate another pulse for the highest-priority pending interrupt.
If more that one is pending, they are serviced in the priority order shown in Figure 9-2,
starting with SUDAV (priority 00) as the highest priority, and ending with EP7-OUT (pri-
ority 15) as the lowest.
EZ-USB TRM v1.9
Important
It is important in any USB Interrupt Service Routine (ISR) to clear the 8051 INT2 inter-
rupt before clearing the particular USB interrupt request latch. This is because as soon
as the USB interrupt is cleared, any pending USB interrupt will pulse the 8051 INT2
input, and if the INT2 interrupt request latch has not been previously cleared the pending
interrupt will be lost.
Chapter 9. EZ-USB Interrupts
Page 9-5