AN2135SC Cypress Semiconductor Corp, AN2135SC Datasheet - Page 106

• Manufacturer Part Number: AN2135SC
• Description: IC MCU 8051 8K RAM 24MHZ 44QFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB®r

Specifications of AN2135SC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: AN213x
• Ram Size: 8K x 8
• Interface: I²C, USB
• Number Of I /o: 8
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1308

use endpoint 2-IN as a double-buffered endpoint. This pairs the IN2BUF and IN3BUF
buffers, although the 8051 accesses the IN2BUF buffer only. The 8051 sets PR2IN=1 (in
the USBPAIR register) to enable pairing, sets IN2VAL=1 (in the IN07VAL register) to
make the endpoint valid, and then uses the IN2BUF buffer for all data transfers. The 8051
should not write the IN3VAL bit, enable IN3 interrupts, access the EP3IN buffer, or load
the IN3BC byte count register.
INnBSY=1 indicates that both endpoint buffers are in use, and the 8051 should not load
new IN data into the endpoint buffer. When INnBSY=0, either one or both of the buffers
is available for loading by the 8051. The 8051 can keep an internal count that increments
on EPnIN interrupts and decrements on byte count loads to determine whether one or two
buffers are free. Or, the 8051 can simply check for INnBSY=0 after loading a buffer (and
loading its byte count register to re-arm the endpoint) to determine if the other buffer is
free.
A bulk IN endpoint interrupt request is generated whenever a packet is successfully trans-
mitted over USB. The interrupt request is independent of the busy bit. If both buffers are
filled and one is sent, the busy bit transitions from 1-0; if one buffer is filled and then sent,
the busy bit starts and remains at 0. In either case an interrupt request is generated to tell
the 8051 that a buffer is free.
EZ-USB TRM v1.9
Note
Bits 2 and 5 must be set to “0” in the AN2122 and AN2126 devices.
6.7
Important Note
If an IN endpoint is paired and it is desired to clear the busy bit for that endpoint, do the
following: (a) write any value to the even endpoint’s byte count register twice, and (b)
clear the busy bit for both endpoints in the pair. This is the only code difference between
paired and unpaired use of an IN endpoint.
Paired IN Endpoint Status
Chapter 6. EZ-USB CPU
Page 6-9