Z9035112PSC Zilog, Z9035112PSC Datasheet
Z9035112PSC
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Z9035112PSC Summary of contents
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... Program ROM and Character Generation ROM (CGROM) in the Z90351 are both programmable. The Z90351 requires ZiLOG’s Z90369ZEM Emulator with its proprietary ZiLOG Developmental Studio (ZDS) software for programing. To view code effects, the emulator uses a ZOSD board that connects directly to a television screen. Refer to Figure 1 ...
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... The Z90356 incorporates the ROM code developed by the customer with the Z90351. Customer code is masked into both program ROM and CGROM. The Z90356 Television Controller with OSD is based on ZiLOG’s Z89C00 RISC processor core. The Z89C00 is a second-generation, 16-bit, fractional, two’s complement CMOS Digital Signal Processor (DSP) ...
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Figure block diagram of the internal structure of the chip. Figure 3 illustrates the pin locations, and Table 1 describes the function of each pin. ...
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SrtÃ6qq…9h‡h 6qq…r†† 9h‡h ...
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Z90356 or Z90351 Top View && && ...
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... The design has been optimized for processing power and silicon space. The Z89C00 used in the Z90356 device has been modified. The multiplier is disabled and is not accessible. However, the X and Y registers in the multiplier are still available and can be used as general-purpose registers. Refer to ZiLOG’s Z89C00 documentation. ...
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The 24-bit ALU has two input ports, one of which is connected to the output of the 24-bit Accumulator. The other input is connected to the 24-bit P-Bus; the upper 16 bits are connected to the 16-bit D-Bus. Several instructions ...
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X and Y are 16-bit general purpose registers 24-bit Accumulator. The output of the ALU is sent to this register. When 16-bit data is transferred into this register, it goes into the 16 MSBs and the least ...
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Pn:b are the pointer registers for accessing data RAM. ( refer to the pointer number refers to RAM bank 0 or 1). They can be read from or written to directly and can ...
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External registers reside on the chip and are used to control the operation of all the peripheral modules in the device. By reading or writing to the fields in the external registers, the user can interact with the peripheral devices ...
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LD A, #(%8000 + 29*256 + %57); write 57 (hex) into the AR29 LD %1FF, A; The DWB and port number are latched for further reading if necessary. To read from the AR, the address must be previously latched by ...
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The addresses in RAM can be specified in one of three ways. Refer to Figure 5. ...
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Q) ; !$% Q ) Q!) 5Q ) È"& È"! È È' 55Q ) È"! È The Z90356 has 64K words of Read Only Memory (ROM) and 1K words of Random Access Memory (RAM). The 64K words mask ROM ...
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CGROM can be placed anywhere in the 64K ROM address space by setting the CGROM address offset register R7(2). This offset is added to the character address before accessing ROM. By modifying the CGROM offset, several fonts can be accessed ...
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The 1K words RAM is organized in four banks of 256 words consisting of 16 bits each. Bankl.0 is always accessible. Bank0.0 is mapped to other bank(s); only one gauge from 0.X is active through bit selection. See Figure 7. ...
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The 32-KHz oscillator circuit in Figure 9 is suggested for proper clock operation 6:,7&+ 6:,7&+ Z90356 XTAL1 XTAL2 6:,7&+ ...
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Reset conditions including addresses and registers are listed in Table 6. ...
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There are two low-power operating modes for Z90356: SLEEP mode and STOP mode. In SLEEP mode, the controller uses the 32.768-KHz clock for the SCLK to reduce power consumption. In STOP mode, the processor is suspended, and the power consumption ...
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W && W ...
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The Z90356 has three external interrupt signals. There are four interrupt sources as follows: • Horizontal sync (H ) SYNC • Vertical sync (V ) SYNC • Capture timer • External event (Port09). All interrupts are vectored. The capture timer ...
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The watch-dog timer resets the CPU when it times out. External register R7(1) controls the watch-dog timer. A clock timer, in real time, generates ticks every 1000, 250, 62.5 or 15.625 ms. External register R5(1) controls the real time clock. ...
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This function employs a 4-bit resolution, flash A-to-D converter. The six-to-one analog input multiplexor and conversion start circuits are controlled by the user program. The 4-bit conversion result is available to be read by the CPU at the end of ...
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Ref– The maximum sampling rate of the ADC converter is 3 MHz. It takes 4 SCLK cycles for valid output data from the ADC to become available. This is especially important if the application uses ...
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NOPs between ADC accesses are omitted. LD SR,%#20; select RegBank1 LD A,EXT4; turn “ADC data packing” mode #%0200; LD EXT4 EXT4; read first ADC sample %0005 LD A, EXT4; read second ADC ...
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The first module, the Master, can be configured for fast (400 kHz) or slow (100 kHz) bit rates and can be used in applications with a single master. The second module, the Slave, supports a 7-bit addressing format with both ...
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! ...
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! ...
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Write R3(0) (Send Data byte) ^[[[[[[[[[[` ...
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R3(0)<0>=1 X…v‡rÃS" Write R3(0) yes If a “Stop” condition is detected at any point, the hardware resets the “Slave” bit 2 (R3(0)<a>) and releases the I C bus. ’r† ...
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The Z90356 provides sophisticated on-screen display features. On-Screen Display has the following two modes: • OSD Used to generate TV control OSD • CCD Used to display Closed Caption information OSD mode provides access to the full set of control ...
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Video RAM CGROM OSD:At7Ch8 Pixels Attr15 2x CCD:Char7 3x orAttr7 Full attrib Memory Rd Shift Register Attribute e s CPU ...
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Closed-caption text can be decoded directly from the composite video signal using the processor’s digital signal processing capabilities and displayed on the screen. The character representation in this mode provides simple attribute control by inserting control characters. Each word ...
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The character scan line from CGROM addressed by the character register is fetched and stored into the CGROM capture register pixel is set displays the foreground color pixel is set ...
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The Z90356 hardware supports the following two different data formats: • OSD mode, R4(3)<d> supports a standard OSD with full set of features. • CCD mode, R4(3)<d> supports reduced features which comply with the recommendations ...
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Shadows, if enabled, are active on both transparent and nontransparent backgrounds. Two bits in the AttributeWR and AttributeRD registers (R2(3)<1:0> and R3(3)<1:0>) control the type of shadow. Refer to Figure 22. The smoothing attribute has been moved to R7(3)<5>. The ...
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The unlatched semi-transparency attribute is controlled by bit [R3(3)<8>]. This bit has one of four possible assignments depending on how it is set up in [R7(3)<7:6>]. The four assignments are underline, semi-transparency, blinking, and CGROM bank select. 1. The semi-transparency ...
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Initialization occurs by setting the Cursor_Info_Load bit R7(3)<4> then writing sequentially to the R3(3) 16-bit parameters (COLOR, HPARAM, VPARAM and CADDR, respectively). The cursor buffer is loaded from ROM at the leading edge of HSYNC wherever the horizontal ...
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AddrN: L0_P15_B0, L0_P14_B0, L0_P13_B0, ... , L0_P1_B0, AddrN+1: L0_P15_B1, L0_P14_B1, L0_P13_B1, ... , L0_P1_B1, AddrN+2: L1_P15_B0, L1_P14_B0, L1_P13_B0, ... , L1_P1_B0, AddrN+3: L1_P15_B1, L1_P14_B1, L1_P13_B1, ... , L1_P1_B1, .................................................. AddrN+2n: ...
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AddrN+3: L0_P15_B1, L0_P14_B1, L0_P13_B1, ... , L0_P1_B1, AddrN+4: L0_P31_B0, L0_P30_B0, L0_P29_B0, ... , L0_P17_B0, L0_P16_B0 AddrN+5: L0_P31_B1, L0_P30_B1, L0_P29_B1, ... , L0_P17_B1, L0_P16_B1 .................................................. AddrN+4n: Ln_P31_B0, Ln_P30_B0, Ln_P29_B0, ... , Ln_P17_B0, Ln_P16_B0 AddrN+4n+1: Ln_P31_B1, Ln_P30_B1, Ln_P29_B1, ... , Ln_P17_B1, Ln_P16_B1 ...
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The Z90356 features a total of 16 color palettes which are fixed and 8 of which are programmable. Palettes are selected by setting R7(3)<3:0>. Fixed palettes are defined in Table 15. 8‚y‚… Qhyr‡‡rà 9r†p…vƒ‡v‚ S Programmable palettes ...
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Basic receiver functions such as color and volume can be controlled directly by six 6-bit pulse-width ...
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Hardware-accelerated byte and nibble shifts significantly reduce software overhead. Shifts are created by assigning one particular RAM location (%1FE) a special meaning. Depending on the R4(1)<e:d> settings data read from this address is either unmodified, rotated 4 bits left, 4 ...
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AND A, #%9FFF #%4000; LD EXT4, A; select “4-bit right rotate” #%3ED7; load A = %3ED7 LD %1FE, A; write A to the RAM LD A, %1FE %73ED LD A,EXT4; turn “hardware-supported rotate” mode ...
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The register file in the Z90356 is organized into four banks that can be selected by writing to bits 5 and 6 (Register Bank Selector bits) in the Status Register of the Z90356 core. All registers are mapped into an ...
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Table 19 defines the bits for Register1–R1(0) Cursor Palette Control Register. Table 20 defines the bits for Register2–R2(0) PLL Frequency ...
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If the master or slave I C interface is enabled, the corresponding I/Os (Port01 and Port02 for the slave, Port11 and Port12 for the master) must be assigned as outputs. ...
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At POR, the PLL frequency data register is preset to %70, which corresponds to the VCO frequency of 12.058 MHz. The PLL_data field can be loaded with any value from %00. This value corresponds to an SCLK = 256*XTAL up ...
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Data written to R3(0)<cb> requires 4 cycles before being applied. Consecutive writings to these bits require at least a 6-cycle delay. The received data is available for reading only when the “busy” ...
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fedcba9876543210 ...
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fedcba9--------- -------876543210 fedcba9876543210 ...
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Table 26 through Table 33 provide bit functions for Bank 1 Control registers. ...
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At POR the disable_clamp bit is set to 1. ...
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The clamp pulse is generated if Enabled (bit <f>) and the SCLK frequency are switched back to PVCO. The SVCO/PVCO flag in R6(1) must be reset to 0 before the current HSYNC, regardless of whether the SVCO is enabled or ...
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Wait for one second (1s) for the 12-MHz PLL to stabilize (about 50000 clock cycles). The delay depends on the external PLL filter and CAN vary significantly. 4. Switch the SCLK to a fast clock (set Fast/Slow bit R1(1)<0> ...
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When a POR, SMR or a WDT reset occurs, the WDT is disabled. The WDT can be reenabled only after the PVCO and SVCO are enabled, and the part is switched into a Fast mode (SCLK = 12 MHz). When ...
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Two bits define the polarity of the HVSYNC signals. Bit <3> defines polarity of the signals when they are configured as outputs (it does not affect the internal HV signals). Bit <1> defines ...
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HSYNC is Leading Edge Active (R4(1)<c> = 1),the actual interrupt is delayed from the leading edge of HSYNC by 72 cycles (~6uS @12MHz). ...
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ADC0 has a signal range from 1.5 to 2.0 V. This field is always connected to the Composite Video Input pin and can be clamped to a Ref– voltage (1.5V). ADC1, ADC2, ADC3, and ADC4 have a signal range from ...
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------98-------- --------7------- ---------6------ ----------54---- ------------32-- --------------10 fedcba9876------ ...
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The H_position field defines the delay between when the Z90356 receives an H-sync and when the H-sync interrupt is executed. Because the On-Screen Display is controlled by software this delay allows fine tuning for On-Screen Display centering. ...
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Use the following procedure when changing from Switching VCO to permanent PVCO while running from the fast clock: Simultaneously set the H_position delay to 0x0, while leaving the No_switch enabled (0), and the SVCO/PVCO left as (0). Wait a ...
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The clamp pulse (defined in R0(1)) is generated only if the SVCO/PVCO switch is set to PVCO before receiving an H SYNC every H . SYNC Table 33 lists the interrupt/WDT for the WST/SMR control register. fed------------- ---cba---------- ------98-------- --------7------- ...
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The final result of the Stop-Mode Recovery (SMR) is RESET. Ports selected for SMR must be assigned as inputs, while the other SMR ports must be assigned as outputs exhibiting an inactive value. ...
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All of the PWMs feature push-pull. Outputs from all PWMs are staged by one PVCO clock. The repetition frequency of the PWM output signals can be calculated from the following equation: F 12MHz PVCO ...
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fe-------------- --dcb----------- -----a98-------- --------76543210 fedcba9876543210 ...
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Table 38 lists the R0(3)- R2(3) character multiplier registers (Read operation). Table 39 lists the R0(3)–R1(3) Shift Registers (Write operation). Table 40 lists the R2(3) Attributes Register (Write operation). ffeeddccbbaa9988 fffeeedddcccbbba 7766554433221100 aa99988877766655 fedcba9876543210 5444333222111000 ...
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Registers R1(3) and R0(3) must be loaded with video data once every 16 cycles. To support smoothing, register R1(3) must be updated every 16 cycles. The current line register is loaded first, followed by next/previous register during the ...
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-edc------------ ----ba9--------- ----ba---------- ------9--------- -------8-------- --------7------- ---------6------ ----------5----- -----------4---- ------------32-- ...
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The attributes register must be loaded 8 cycles after the current line register R0(3) is loaded. ...
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... CGROM data is latched, core operations are resumed. When a control character code is loaded into the attribute_data register, the CGROM data from address 0000 hex is fetched. Therefore, ZiLOG recommends placing a space character at location 0000 hex in CGROM. Refer to Table 43 through Table 46 for the various VRAM data formats loaded ...
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f--------------- -edc------------ ------ba9------- --------ba------ -------9--------- -------8-------- --------76543210 ...
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Smoothing is supported for double size (x2) and triple size (x3) characters only. At reset, the background color in OSD mode is black. Foreground color, background color, blinking and italic attributes are ...
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7------- -6543210 ...
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In CCD mode, each character occupies 8 bits (one byte) in VRAM. The CCD characters must be mapped into a 16-bit VRAM data field. The hardware supports compressed character placement in VRAM. Each word ...
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Combining display and control characters generates a CCD or OSD according to FCC specification. Refer to Table 47. fe-------------- --d------------- ...
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R2(3), causing the screen character to be underlined. The Italic shift field defines a delay of video data used to generate italic characters. The firmware decrements by 1 (the ...
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At POR the palette control register is reset to 0. Table 50 lists the bits for the output palette control register. ...
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At POR the Output palette register is set to 0 for digital output. Table 15 is the look-up table for the color palettes. ...
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The processor instruction set consists of 30 basic instructions optimized for high code density and reduced execution time. Single-cycle instruction execution is possible on most instructions. The format for Op Codes and addressing modes is provided in the ...
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To access the operands for the DSP, use the Register Pointers, Data Pointers, Hardware Registers, Direct Addressing, Immediate Data and Memory. There are nine distinct types of instruction operands. Table 59 and Table 60 list instructions. ...
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The register pointer mode is used for loading the pointer with the appropriate RAM address. This address references the RAM location that stores the requested data. The pointer can also be used to store 8-bit data when used as a ...
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Each instruction type has a unique Op Code and format to differentiate various instructions. Different operations also have unique formats. The variables a, op cc, am, fm, rp are used ...
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The values in a series of bits in a register form patterns called codes include the following: • Condition Codes • Accumulator Modification Code • Flag Modification Codes • Source/Destination Field Designators • Register Pointer/Data Pointer The following tables list ...
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Accumulator modification codes determine the type of modification made to the value in the accumulator. See Table 62. Condition codes are also used with CALL, and JUMP instructions. 0000 0001 0010 ...
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Register pointers and data pointers provide convenient access to data. The pointers are a source or destination field in instructions. Specific bit codes are listed in Table 64. The register pointer offers optional incrementing ...
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Data pointers are automatically incremented when accessing program memory (for example @D0:0) and do not require an incrementing option. Code in xx11 format is designated for a data pointer when source or destination format is used. Additional source ...
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The Variables a, op cc, am, fm, rp are used in the instruction format to depict bits determined by the instruction. 2. The General Instruction Format requires an Op Code, RAM bank bit, destination and source ...
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Several instructions provide various addressing modes to obtain operands; therefore, the same instruction can have several different formats depending on the addressing mode. 2. The variables a, op ce, am, fm, rp are used in the ...
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1001010 00000 0010 1001010 00000 0100 1001010 00000 1000 1001010 00000 0011 1001010 00000 0101 1001010 00000 1001 ...
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1000011 011111111 1010011 011111111 0110011 011111111 0000111 000010010 00011 101 11111010 ...
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JUMP CALL The DSP can be executed with single cycle instruction using the independent data memory and program memory buses offered by the modified Harvard architecture and pipeline instruction. This method provides overlapping of instruction fetch and execution cycles. Figure ...
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In two-byte instructions, the second byte is being fetched while the first byte is executing. Because the processor knows that the instruction is a JUMP or CALL, the second byte is transferred to the program counter and the correct address ...
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1011001 1010001 1010100 1010101 1010001 1010001 1010000 0010100 0010100 1001010 1001010 1001010 0111001 0110001 0110101 0110011 0110001 0110000 0110100 1001000 1001000 1001000 1001000 0100110 0100110 ...
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0000000 0000001 0001001 0000001 0000101 0000011 0000111 0000100 0001100 0001010 0000110 0000010 0001001 0000001 0000100 0100101 0000101 0000001 0000000 ...
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1001000 1001000 0000000 1101001 1100001 1100100 1100101 1100011 1100001 1100000 0001010 0000100 0000010 0000000 0001001 0000001 0000001 0000000 0000100 0100101 0000101 0000000 1001000 1001000 1001000 1001000 ...
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The DSP instruction set consists of 30 basic instructions, optimized for high-code density and reduced execution time. Single-cycle instruction ...
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Each Assembly Instruction includes an example for each addressing mode available for the specific instruction. The mnemonics listed in Table 75 are used in the instruction format. ABS A ABS <cc> ...
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ABS <cc>, A ABS A If ACC < 0 then -(ACC) -> ACC Flags: N: Set if the accumulator has 800000H (see below). If the contents of the accumulator are determined to be less then 0 (a negative number), the ...
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ABS <cc>, A Initialization: Accumulator contains 456400H Instruction: ABS MI, A Result: Accumulator contains 456400H This example uses one word of memory and executes in one machine cycle. The condition code (negative bit) is not set because the accumulator value ...
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ADD A, ADD A, ADD A, ADD A, ADD A, ADD A, ADD A, ACC + <source> -> ACC Flags: C Set if carry from the most significant bit is found. Set if result in the accumulator is negative. N: ...
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Initialization: Accumulator contains 123456H P0:0 contains 4DH RAM Bank1: 4DH contains 8746H Instruction: ADD A, @P0:0 Result: A contains 997A56H @P0:0 contains 746H This example uses one word of memory and executes in one machine cycle. The pointer P0:0 contains ...
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This example uses two words of memory and executes in two machine cycles. The immediate operand 0C12H is added to the accumulator to obtain the sum 123400H + 0C1200H = 1E4600H. ADD A,<hwregs> Initialization: Accumulator contains 23400H Register X contains ...
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ADD A,<dregs> Initialization: Accumulator contains 123400H D0: 1 contains 8746H Instruction: ADDA,D0:1 Result: A contains 997A00H D0: 1 contains 8746H This example uses one word of memory and executes in one machine cycle. The contents of the data pointer D0:1 ...
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AND A, <regind> AND A, <memind> AND A, <limm> AND A, <hwregs> AND A, <direct> AND A, <pregs> AND A, <dregs> AND A, <simm> <accumulator>. AND.<source> —> <accumulator> Flags: N: Set if accumulator result is less than 0. Set if ...
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Result: Accumulator contains 020400H This example uses one word of memory and executes in one machine cycle. The data in RAM Bank1, referenced by RAM pointer 0, is stored in the specified accumulator using an AND instruction 123456H.AND.874600H = 020400H. ...
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Instruction: AND A, #%1F Result: Accumulator contains 001400H This example uses one word of memory and executes in one machine cycle. The data in the immediate field and the contents of the accumulator are processed with an AND instruction. 123456H.AND.001F00H ...
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This example uses one word of memory and executes in one machine cycle. Use an AND instruction to send the contents of the pointer register P0:0 to the accumulator 123400H.AND.005600H = 001400H. The Pointer Register is connected to the lower ...
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CALL <cc>,<direct> CALL <direct> —> STACK 16-Bit Address —> PC Flags: None The current Program Counter (PC) register content is incremented by two and placed on the stack. The address of the specified label in the CALL ...
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Result: PC contains F234H Stack Level 0 contains 1FFDH Stack Level 1 contains 0025H This example uses two words of memory and executes in two machine cycles. The call to the subroutine FFT2 places PC+2 (1 FFDH) on the stack. ...
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The subroutine address is then placed in the PC register. The processor executes the next instruction addressed by the PC, the FFT2 subroutine. ...
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CCF Zero —> Carry Bit Flags: C: Set to 0. The Clear Carry Flag instruction resets the carry flag with a 0. CCF Initialization: SR contains 3000H Instruction: CCF Result: SR contains 2000H C contains 0 This example uses one ...
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CIEF Zero —> IE bit Flags: IE: Set to 0. The Clear Interrupt Enable Flag instruction sets the IE flag to 0. CIEF Initialization: SR contains 3080H Instruction: CIEF Result: SR contains 3000H IE contains 0 This example uses one ...
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COPF Zero —> OP bit Flags: P: Set to 0. The Clear Overflow Protection Flag instruction resets the OP flag to 0. COPF Initialization: SR contains 0100H Instruction: COPF Result: SR contains 0000H OP contains 0 This example uses one ...
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<source> —> set appropriate status bits Flags: C: Set if carry is required for operation. Set if operands are equal. Z: Set ...
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CP A, <regind> Initialization: A contains 7A2500H P2:1 contains A4H RAM Bank1: A4H contains 5463H Instruction @P2:1 Result: A contains 7A2500H SR contains 1000H This example uses one word of memory and executes in one machine cycle. The ...
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Initialization: A contains 7A2500H Instruction #%7A25 Result: A contains 7A2500H SR contains 3000H This example uses two words of memory and executes in two machine cycles. The immediate operand is compared to the accumulator. Because they are equal, ...
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Initialization: Accumulator contains 123400H P0:0 contains 56H Instruction P0:0 Result: Accumulator contains 123400H SR contains 1000H This example uses one word of memory and executes in one machine cycle. The contents of the pointer register P0:0 are compared ...
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DEC A DEC <cc>, A ACC - 1 —> ACC Flags: C: Set if carry is required for operation Set if result Set if decrement results in a value less then 0. N: Set if upper (7FFFFFH) ...
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Instruction: DEC MI, A Result: A contains 7A2500H This example uses one word of memory and executes in one machine cycle. Because the accumulator is not negative, the decrement instruction is not executed. ...
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INC <cc>, A INC A ACC + 1 —> ACC Flags: C: Set if carry is required for operation. Set if result Set if results in a value less then 0. N: Set if upper (7FFFFFH) or ...
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Instruction: INC A Result: A contains 7A2501H This example uses one word of memory and executes in one machine cycle. The value in the accumulator is incremented by 1. ...
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JP <cc>, JP <direct> 16-Bit address —> PC Flags: None The instruction places the address of the referenced ROM location in the Program Counter (PC). Because the processor obtains its next instruction address from the PC, the processor jumps to ...
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JP <direct> Initialization: Routine 1 address contains 1455H PC contains 1343H Instruction: JP Routine 1 Result: PC contains 1455H This example uses two words of memory and executes in two machine cycles. The value in the program counter is replaced ...
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<direct>, LD <hwregs> <dregs>, LD <hwregs> <pregs>, LD <hwregs> <pregs>, LD <hwregs> <regind>, LD <hwregs> <hwregs>, LD <hwregs>, <source> —> <destination> Flags: ...
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The LOAD command provides the ability to transfer data to several different locations in the processor including hardware registers, accumulator, stack, pointers and memory. All transfers across the various internal buses are transparent to the user load using ...
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Result: A contains OC1 200H P0:0 contains 21H RAM Bank0: 21H contains 247BH This example uses one word of memory and executes in three machine cycles. The pointer P0:0 contains the RAM register location (21H). The contents of this register ...
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This example uses one word of memory and executes in one machine cycle. Register F3H is loaded to the accumulator. An equivalent instruction is LD A,243 (F3H = 243 decimal <dregs> Initialization: Accumulator contains123400H D0: 1 contains 8746H ...
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LD <pregs>, <simm> Initialization: P2:0 contains 2FH RAM Bank0: 3FH contains 254645H Instruction: LD P2:0, #%3F Result: P2:0 contains 3FH RAM Bank0: 3FH contains 254645H This example uses one word of memory and executes in one machine cycle. The immediate ...
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Initialization: P2:0 contains 2FH X Register contains 8B87H Instruction: LD X,P2:0 Result: P2:0 contains 2FH X Register contains This example uses one word of memory and executes in one machine cycle. The contents of the P2:0 pointer (2FH) are loaded ...
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Initialization: EXT7 Register contains 8B87H Accumulator contains 77B6H ROM 77B6H contains 387DH Instruction: LD EXT7, @A Result: EXT7 Register contains 387DH Accumulator contains 77B6H This example uses one word of memory and executes in one machine cycle. The contents of ...
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Result: X Register contains 5463H This example uses one word of memory and executes in one machine cycle. Indirect addressing through the pointer registers provides access to RAM data. The data in RAM bank 1, register A4 is transferred to ...
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NEG A NEG <cc>, A -ACC —> ACC Flags: N Set if result is a negative number. Two special cases are ACC contains 000000 after execution, then N and 0V are cleared, and Z and C are set ...
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NEG <cc>, A Initialization: A contains 000111H Carry bit contains 1 Instruction: NEG C, A Result: A contains FFFEEFH This example uses one word of memory and executes in one machine cycle. ...
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NOP PC+ 1—> PC Flags: None The NOP instruction causes the processor to continue operation for one cycle without affecting previous registers and I/0. ...
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OR A, <regind> <memind> <limm> <hwregs> <direct> <pregs> <dregs> <simm> ACC .OR. source —> ACC Flags: N Set If result in accumulator is negative. Set If ...
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Initialization: Accumulator contains 3264A0H P0:0 contains E2H RAM Bank0: E2H contains 1126H Instruction @P0:0 Result: A contains 336600H This example uses one word of memory and executes in one machine cycle. Use an OR instruction to reference the ...
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POP <pregs> POP <dregs> POP <regind> POP <hwregs> STACK 0 —> <destination> Stack n —> Stack N-1 Flags: None The current value of the stack is copied to the specified register. Because the stack is a last-in, first-out (LIFO) hard-wired ...
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This example uses one word of memory and executes in one machine cycle. The destination of Stack 0 (item on top of stack) is P0:0. The 8-LSBs of the data in stack 0 are loaded into P0:0. At transfer, Stack ...
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Initialization: Stack 1 contains 0426H Stack 0 contains 0C06H X Register contains 089CH Instruction: POP X Result: Stack 0 contains 0426H X Register contains 0C06H This example uses one word of memory and executes in one machine cycle. The destination ...
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PUSH <pregs> PUSH <dregs> PUSH <memind> PUSH <accind> PUSH <regind> PUSH <hwregs> PUSH <direct> PUSH <limm> <source> —> Stack Stack n —> Stack n+ 1 Flags: None The contents of the specified register are placed on the stack. Because the ...
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Initialization: Stack 0 contains 0C06H P1:1 contains A4H Instruction: PUSH P1:1 Result Stack 1 contains 0C06H Stack 0 contains 00A4H This example uses one word of memory and executes in one machine cycle. The pointer P1:1 contains the 8-bit value ...
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Using OR A,@@P0:0+ performs the same operation and also increments the P0:0 content to A5H. PUSH <accind> Initialization: Stack 1 contains 0426H Stack 0 contains 0C06H Accumulator contains 42A4H ROM address 42A4H contains 4C45H Instruction: PUSH @A Result Stack 1 ...
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Instruction: PUSH X Result: Stack 1 contains 0C06H Stack 0 contains 42A4H This example uses one word of memory and executes in one machine cycle. The data in the X register is pushed onto the stack. At transfer, Stack 0 ...
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RET Stack 0 —> PC Stack n —> Stack n-1 Flags: None The current stack information is popped from the stack and placed in the Program Counter (PC) register. The jump is made from the subroutine via the PC. RET ...
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<cc>,A C <= 23 ------------ < ---------- 8 <= C Flags: N Set if result of accumulator is negative Set if result is zero. Z Set if MSB is set before rotate. C The upper 16 bits ...
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RL <cc>, A Initialization: A contains 226A84H Carry bit contains 0, Z=0 Instruction Result: A contains 226A84H This example uses one word of memory and executes in one machine cycle. The condition code 0 is not set; ...
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<cc> =>23 ---- > => -> —> discarded Flags: N Set if result of accumulator is negative. Set if result Set if LSB is set before ...
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Initialization: A contains 226A84H Carry bit contains 0, Z=0 Instruction Result: A contains 226A84H This example uses one word of memory and executes in one machine cycle. The condition code 0 is not set; therefore, the instruction ...
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SCF 1 —> Carry Bit Flags: C Set to 1. The Set Carry Flag instruction places a one in the carry bit (bit 12 of the Status Register). SCF Initialization: SR contains 2000H Instruction: SCF Result: SR contains 3000H C ...
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SIEF 1 —> IE bit Flags: None The instruction places bit 7 of the status register and is used to enable interrupts. SIEF Initialization: SR contains 3000H Instruction: SIEF Result: SR contains 3080H IE contains 1 This ...
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SLL A SLL <cc>, A discarded <— C < < <= 0 Flags: N Set if result of accumulator is negative (bit 23 set to 1). Set if result is 0. ...
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Initialization: A contains 226A84H Carry bit contains 0 Instruction: SLL MI, A Result: A contains 226A84H This example uses one word of memory and executes in one machine cycle. The condition code N is not set, and the instruction is ...
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SOPF 1 —> OP bit Flags: None The Set Overflow Protection Flag instruction places a one in bit 8 of the status register ALU operation exceeds the limits of the processor, the overflow protection sets the overflow flag ...
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SRA A SRA <cc> => 23 --- > ---- 0 => discarded Flags: N Set if result of accumulator is negative. Set if result Set if LSB is set before the shift. C All 24 ...
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SRA <cc>, A Initialization: A contains 226A84H Carry bit contains 0, N=0 Instruction: SRA A Result: A contains 113542H Carry bit contains 0 This example uses one word of memory and executes in one machine cycle. The condition code is ...
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SUB A, <regind> SUB A, <memind> SUB A, <limm> SUB A, <hwregs> SUB A, <direct> SUB A, <pregs> SUB A, <dregs> SUB A, <simm> ACC – (Source) —> ACC Flags: C Set if a carry from the most significant bit ...
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Initialization: Accumulator contains 874600H P0: 1 contains 45H RAM Bank1: 45H contains 1234H Instruction: SUB A, @P0:1 Result: A contains 751200H @P0:1 contains 1234H This example uses one word of memory and executes in one machine cycle. The contents of ...
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This example uses two words of memory and executes in two machine cycles. The immediate operand 8746H is subtracted from the accumulator. 874600H - 123400H = 751200H. SUB A, <hwregs> Initialization: Accumulator contains 874600H Register X contains 1234H Instruction: SUB ...
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SUB A, <pregs> Initialization: Accumulator contains 874600H P0:0 contains 56H Instruction: SUB A, P0:0 Result: Accumulator contains 86F000H This example uses one word of memory and executes in one machine cycle. The contents of pointer register P0:0 are subtracted from ...
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XOR A, <regind> XOR A, <memind> XOR A, <limm> XOR A, <hwregs> XOR A, <direct> XOR A, <pregs> XOR A, <dregs> XOR A, <simm> A.XOR.<operand> —> A Flags: C Set if carry from the most significant bit is performed. Set ...
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Initialization: Accumulator contains 005600H P0:0 contains 00H RAM Bank0: 00H contains 1234H Instruction: XOR A, @P0:0 Result: A contains 126200H This example uses one word of memory and executes in one machine cycle. The pointer is used for memory indirect ...
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Result: A contains 2342A0H SR contains 0000H This example uses two words of memory and executes in two machine cycles. Perform an XOR instruction on the immediate data. XOR A, <hwreg> Initialization: A contains 3264A0H SR contains 0000H BUS contains ...
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W && && && ...
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5± & 5± 5 5± 5± 5± 5± 5 5± 5 5± 5± 5 5± 5 5± 5± 5 5± 5 5± 5± 5 5± 5 ...
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Table 81 lists the AC characteristics. – – – – – – – – ...
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The RGB outputs in analog mode are controlled current sources with an internal load. These outputs display gamma-corrected, V Table 83, and Figure 28 prorated characteristics. See Table 82, CC ...
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The Z90356 provides the ability to • decode closed-caption transmissions • display characters on the screen • manipulate analog and digital control circuits • monitor keypad and infrared signals directly • generate OSD if the Z90356 receives vertical and horizontal ...
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The Z90356’s STOP mode suspends processor clocking for a power-down. Program, display, and character graphics memory are on the chip, eliminating the requirement for external memory components. Characters can be displayed as two ...
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Detail A S Controlling dimension in inches Optional end lead config Detail A ...
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... I f there are any problems while operating this product, or any inaccuracies in the specification, please copy and complete this form, then mail or fax it to ZiLOG. Suggestions welcome! ZiLOG System Test/Customer Support 910 E. Hamilton Avenue, Suite 110, MS 4–3 Campbell, CA 95008 Fax: (408) 558-8536 Provide a complete description of the problem or suggestion ...