SL811HST-AXC Cypress Semiconductor Corp, SL811HST-AXC Datasheet - Page 9

• Manufacturer Part Number: SL811HST-AXC
• Description: IC USB HOST/SLAVE CTRLR 48LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL811HST-AXC

• Package / Case: 48-LQFP
• Applications: USB Host/Slave Controller
• Controller Series: USB-Hosts
• Ram Size: 256 x 8
• Interface: USB
• Number Of I /o: 8
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 65°C
• Mounting Type: Surface Mount
• Operating Supply Voltage: 3 V
• Supply Current (max): 25 mA
• Maximum Operating Temperature: + 65 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Core Size: 8 Bit
• Ram Memory Size: 256Byte
• Cpu Speed: 48MHz
• Embedded Interface Type: I2C, USB
• Digital Ic Case Style: TQFP
• Supply Voltage Range: 3V To 3.45V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3662 - KIT DEVELOPMENT EZ-811HS
• Core Processor: -
• Program Memory Type: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1721; SL811HST-AXC

Document 38-08008 Rev. *D
Interrupt Enable Register [Address = 06h]. The SL811HS
provides an Interrupt Request Output, which is activated for a
number of conditions. The Interrupt Enable register allows the
user to select conditions that result in an interrupt that is issued
to an external CPU through the INTRQ pin. A separate
Interrupt Status register reflects the reason for the interrupt.
Enabling or disabling these interrupts does not have an effect
on whether or not the corresponding bit in the Interrupt Status
register is set or cleared; it only determines if the interrupt is
Table 13. Interrupt Enable Register [Address 06h]
USB Address Register, Reserved, Address [Address = 07h]. This register is reserved for the device USB Address in Slave
operation. It should not be written by the user in host mode.
Registers 08h-0Ch Host-B registers. Registers 08h-0Ch have the same definition as registers 00h-04h except they apply to
Host-B instead of Host-A.
Bit Position
Reserved
Bit 7
7
6
5
4
3
2
1
0
Detect/Resume
Device Detect/Resume Enable Device Detect/Resume Interrupt.
Inserted/Removed
SOF Timer
Reserved
Reserved
USB-B DONE
USB-A DONE
Device
Bit 6
Bit Name
Reserved
Removed
Inserted/
Bit 5
‘0’
When bit 6 of register 05h (Control Register 1) is equal to ’1’, bit 6 of this register enables
the Resume Detect Interrupt. Otherwise, this bit is used to enable Device Detection
status as defined in the Interrupt Status register bit definitions.
Enable Slave Insert/Remove Detection is used to enable/disable the device
inserted/removed interrupt.
1 = Enable Interrupt for SOF Timer. This is typically at 1 mS intervals, although the
timing is determined by the SOF Counter high/low registers.
To use this bit function, bit 0 of register 05h must be enabled and the SOF counter
registers 0E hand 0Fh must be initialized.
‘0’
‘0’
USB-B Done Interrupt (see USB-A Done interrupt).
USB-A Done Interrupt. The Done interrupt is triggered by one of the events that are
logged in the USB Packet Status register. The Done interrupt causes the Packet Status
register to update.
Function
SOF Timer
Bit 4
routed to the INTRQ pin. The Interrupt Status register is
normally used in conjunction with the Interrupt Enable register
and can be polled in order to determine the conditions that
initiated the interrupt (See the description for the Interrupt
Status Register). When a bit is set to ’1’ the corresponding
interrupt is enabled. So when the enabled interrupt occurs, the
INTRQ pin is asserted. The INTRQ pin is a level interrupt,
meaning it is not deasserted until all enabled interrupts are
cleared.
Reserved
Bit 3
Reserved
Bit 2
USB-B
DONE
Bit 1
SL811HS
Page 9 of 32
USB-A
DONE
Bit 0