SL811 Cypress Semiconductor Corporation., SL811 Datasheet
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... SL811S/T USB Dual Speed Slave Controller Data Sheet This document is subject to change without notice Cypress Semiconductor Corporation Document #: 38-08009 Rev. ** • 3901 North First Street • San Jose SL811S/T • CA 95134 • 408-943-2600 Revised October 1, 2001 ...
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... SL811S/T PHYSICAL CONNECTION .......................................................................................... 14 6.1 Pin Layout .................................................................................................................................... 15 6.2 28-PIN PLCC Mechanical Dimensions ....................................................................................... 15 6.3 SL811S USB Controller, Pin Descriptions ................................................................................. 15 6.4 SL811ST Pin Layout .................................................................................................................... 17 6.5 SL811ST 48-Pin LPQFP Mechanical Dimensions ..................................................................... 18 6.6 SL811ST USB Controller, Pin Descriptions .............................................................................. 18 7.0 ELECTRICAL SPECIFICATIONS ................................................................................................. 20 7.1 Absolute Maximum Ratings ........................................................................................................ 20 7.1.1 Recommended Operating Condition ................................................................................................ 20 Document #: 38-08009 Rev. ** TABLE OF CONTENTS SL811S/T ...
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... I/O Read Cycle .................................................................................................................................... 23 7.5.3 SL811S DMA Write Cycle ................................................................................................................... 24 7.5.4 SL811S DMA Read Cycle ................................................................................................................... 25 7.5.5 Reset Timing ....................................................................................................................................... 26 7.5.6 Clock Timing Specifications .............................................................................................................. 26 8.0 REVISION HISTORY ..................................................................................................................... 27 Figure 4-1. 48-MHz Crystal Circuit ..................................................................................................... 8 Figure 4-2. 12-MHz Crystal Circuit. .................................................................................................... 9 Figure 6-1. SL811S USB Controller—Pin layout ............................................................................. 15 Document #: 38-08009 Rev. ** TABLE OF CONTENTS (continued) LIST OF FIGURES SL811S/T Page ...
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... Cypress products, expressly or by implication. Cypress’s products are not authorized for use as critical components in life support devices or systems. SL811S and SL811ST are trademarks of the Cypress Semiconductor Corporation. All other product names and trademarks are registered trademarks of their respective owners. Document #: 38-08009 Rev. ** ...
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... USB Controller incorporates USB Serial Interface functionality along with internal drivers and receivers that connect directly to the USB interface connector. The SL811S/T supports and operates in USB full speed mode Mbits per second and in USB Slow speed mode at 1.5 Mbits per second. ...
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... Data Port, Interface to external Micro-Processor The SL811S/T Data Port interface provides an 8-bit bidirectional data path with appropriate control signals such as CS, RD, WR, A0 and INTR lines. This feature enables it to interface to any external processor or controller (Intel, Motorola, TI, Analog Devices, etc.). The control Read and Write signals, Chip Select and a single address line A0, with the 8-bit data bus, support both programmed I/O or Memory mapped I/O designs ...
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... PLL Clock Generator A 48-MHz external crystal can be used with the SL811S/T. Two pins, X1 and X2, are provided to connect a low cost crystal circuit to the device (refer to Figure 4-1 external 48-MHz clock source is available in the application, it may be used instead of the crystal circuit by connecting directly to the X1 input pin. ...
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... X1 Document #: 38-08009 Rev MHz, series, 20-pF load Cbk 0.01 F Lin 2.2 - 3.3 H Figure 4-1. 48-MHz Crystal Circuit SL811S 100 Cout 22 pF Page ...
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... The SL811S/T can signal a wake-up to the Host USB device, providing the Pull-up resistor remains powered during the Suspend time. A register control bit allows the SL811S/T to output a ‘K’ State on the USB to signal the Host. See Force Function description in the Control Register Section. If the pull-up is powered down during Suspend, restoring power to the pull-up will signal a device connect to the USB host ...
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... Upon completion of a transfer to an endpoint, the 'next data set' bit indicates whether set 'a' or 'set 'b' will be in effect next. The 'armed' bit of the next data set will indicate whether the SL811S/T is ready for the next transfer without interruption ...
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... Endpoint Base Length The Endpoint Base Length is the maximum packet size for Out transfers from the Host. Essentially, this designates the largest packet size that can be received by the SL811S/T. For Transfers In to Host, Base Length designates the size of the data packet to be sent. ...
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... Overall Enable for transfers. '1' enables, '0' disables. Enable DMA Operation when ‘1’. Disable = ‘0’. DMA transfer direction bit. Set ‘1’ for DMA read cycles from SL811S, Set ‘0’ for DMA write cycles. J-K Force State Bit 0. [See Force State Table] J-K Force State Bit 1. Speed Select. ‘ ...
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... Interrupt Enable Register, Address [06h] 5.4.2 The SL811S/T provides an Interrupt Request Output that is activated resulting from a number of conditions. The Interrupt Enable Register allows the user to select activities that will generate the Interrupt Request. A separate Interrupt Status Register is provided. It can be read in order to determine the condition that initiated the interrupt. (See Interrupt Status Register description). ...
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... Register contains the low order 8-bits of DMA count. DMA total count is the total number of bytes to be transferred between a peripheral to the SL811S/T. The count may sometimes require up to 16-bits, thus the count is represented in two registers: Total Count Low, and Total Count High. EP3 is only supported with DMA operation. ...
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... PLCC Mechanical Dimensions 6.2 6.3 SL811S USB Controller, Pin Descriptions The SL811S package is a 28-pin PLCC. The device requires a 3.3VDC and a +3.3 VDC (VDD2) power supply for the USB transceiver. The SL811S requires an external MHz crystal or Clock. Document #: 38-08009 Rev. ** nDACK VDD1 ...
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... Write Strobe Input. An active low input used with nCS to write to registers/data memory. Active low SL811S Chip select. Used with nRD and nWD when accessing SL811S. Clock Mode. Enables DPLL 4x Multiplier for use with 12-MHz Clock. Power for USB Transceivers. Can be connected to Vdd1. ...
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... A simple 3.3V voltage source +5V (USB R1 45 Ohms 3.9v, 1N52288CT-ND GND 6.4 SL811ST Pin Layout The diagram below shows the pin assignments for SL811ST 48-pin LPQFP Package. Document #: 38-08009 Rev Zener +3.3 V (VDD2) Sample Generator 6/67 SL811S/T Page ...
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... SL811ST 48-Pin LPQFP Mechanical Dimensions 6.6 SL811ST USB Controller, Pin Descriptions The SL811ST is packaged in a 48-Pin LPQFP. The device requires 3.3VDC or +5VDC (VDD1) and a +3.3 VDC (VDD2) power supply. Average typical current consumption is less than 22 mA for 3.3 V. The SL811ST requires an external 48-MHz Crystal or Clock. ...
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... Document #: 38-08009 Rev. ** Pin Description SL811ST Device VDD Power. 12/48 MHz Clock or External Crystal X1 connection. External Crystal X2 connection. SL811ST Device active low reset input. Active High Interrupt Request output to external controller. SL811ST Device Ground. Data 0. Microprocessor Data/(Address) Bus Data 1 ...
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... Electrical Specifications 7.1 Absolute Maximum Ratings This section lists the absolute maximum ratings of the SL811S. Stresses above those listed can cause permanent damage to the device. Exposure to maximum rated conditions for extended periods can affect device operation and reliability. Storage Temperature Voltage on any pin with respect to ground ...
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... Impedance Values includes an external resistor of 33–42 Ohms ±1%. USBX Document #: 38-08009 Rev. ** Description = 4 mA –4 mA) OH Min. 0.2V 2.0V 2.8V 0.0V 33 Ohms 33 Ohms Min. Typical Max. –0.3V 0.8V 2.0V 6.0V 0.4V 2. ± 4 [8] Typical 42 Ohms 42 Ohms At Full Speed. SL811S/T Max. 0.8V 0. Page ...
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... Note: 10. I/O Write Cycle Time in Auto Inc Mode is 150 ns minimum. Document #: 38-08009 Rev. ** twr twahld twdhld Register or Memory Address twshld Description Min [10] asserted 85 ns twdsu twdhld DATA Tcscs See Note. Typical [10] SL811S/T Max. Page ...
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... Read cycles providing the nRD line is cycled. I/O Write Cycle Time in Auto Inc Mode is 150 ns minimum. Document #: 38-08009 Rev. ** twr twahld trdp twdhld Register or Memory Address trcsu I/O Read Cycle from Register or Memory Buffer Description [11] SL811S/T tracc trdhld DATA trshld Tcscs *Note Min. Typical ...
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... SL811S DMA Write Cycle 0 Parameter tdack nDACK low tdwrlo nDACK to nWR low delay tdakrq nDACK low to nDRQ high delay tdwrp nWR pulse width tdhld Data hold after nWR high tdsu Data set-up to nWR strobe low ...
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... SL811S DMA Read Cycle 0-D 7 tdaccs Parameter Description tdack nDACK low tddrdlo nDACK to nRD low delay tdckdr nDACK low to nDRQ high delay tdrdp nRD pulse width [12] tdhld Date hold after nDACK high tddaccs Data access from nDACK low ...
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... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. tioact RESET TIM ING Description Min. 16 clocks 16 clocks tlow tfall CLOCK TIMING Min. 20 45% SL811S/T Typical Max. trise Typical Max. 20 55% Page ...
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... Revision History Document Title: SL811HS/T USB Dual Speed Slave Controller Data Sheet Document Number: 38-08009 ISSUE REV. ECN NO. DATE ** 110851 12/21/01 Document #: 38-08009 Rev. ** ORIG. OF CHANGE DESCRIPTION OF CHANGE BHA Converted to Cypress Format from ScanLogic SL811S/T Page ...