CY7C63413C-PVXC Cypress Semiconductor Corp, CY7C63413C-PVXC Datasheet - Page 24

• Manufacturer Part Number: CY7C63413C-PVXC
• Description: IC MCU 8K USB LS PERIPH 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63413C-PVXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C634xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 32
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• No. Of I/o's: 32
• Ram Memory Size: 256Byte
• Cpu Speed: 12MHz
• No. Of Timers: 2
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 4V To 5.25V
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: USB
• Rohs Compliant: Yes
• Processor Series: CY7C63xx
• Core: M8B
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: PS2, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 1
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P02
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1852

The response of the SIE can be summarized as follows:
The In and Out PID status is updated at the end of a transaction.
Document #: 38-08027 Rev. *E
1. the SIE will only respond to valid transactions, and will ignore
2. the SIE will generate IRQ when a valid transaction is
3. an incoming Data packet is valid if the count is <= 10 (CRC
4. a Setup will be ignored by all non-Control endpoints (in appro-
5. an In will be ignored by an Out configured endpoint and vice
Encoding
End Point
Mode
3
Legend:
non-valid ones;
completed or when the DMA buffer is corrupted
inclusive) and passes all error checking;
priate modes);
versa.
2
1
0
Token
Setup
In
Out
Figure 7. Decode table
Properties of incoming packet
count
The number of received bytes
UC: unchanged
x: don’t care
available for Control endpoint only
buffer
The quality status of the DMA buffer
The validity of the received data
dval
forTable
DTOG
TX: transmit
RX: receive
28: “Details of Modes for Differing Traffic Conditions”
Status bits
DVAL
COUNT
The Setup PID status is updated at the beginning of the Data
packet phase.
The entire EndPoint 0 mode and the Count register are locked
to CPU writes at the end of any transaction in which an ACK is
transferred. These registers are only unlocked upon a CPU read
of these registers, and only if that read happens after the
transaction completes. This represents about a 1-s window to
which to the CPU is locked from register writes to these USB
registers. Normally the firmware does a register read at the
beginning of the ISR to unlock and get the mode register
information. The interlock on the Mode and Count registers
ensures that the firmware recognizes the changes that the SIE
might have made during the previous transaction.
TX0: transmit 0-length packet
Set-
up
PID Status bits
In
Out
What the SIE does to Mode bits
Acknowledge phase completed
ACK
End Point
Mode
3
2 1 0
CY7C63413C
CY7C63513C
CY7C63613C
Interrupt?
Re-
sponse
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