CY7C63413C-PVXC Cypress Semiconductor Corp, CY7C63413C-PVXC Datasheet - Page 17

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CY7C63413C-PVXC

Manufacturer Part Number
CY7C63413C-PVXC
Description
IC MCU 8K USB LS PERIPH 48-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
M8™r
Datasheets

Specifications of CY7C63413C-PVXC

Applications
USB Microcontroller
Core Processor
M8B
Program Memory Type
OTP (8 kB)
Controller Series
CY7C634xx
Ram Size
256 x 8
Interface
PS2, USB
Number Of I /o
32
Voltage - Supply
4 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-SSOP
No. Of I/o's
32
Ram Memory Size
256Byte
Cpu Speed
12MHz
No. Of Timers
2
Digital Ic Case Style
SSOP
Supply Voltage Range
4V To 5.25V
Core Size
8 Bit
Program Memory Size
8KB
Embedded Interface Type
USB
Rohs Compliant
Yes
Processor Series
CY7C63xx
Core
M8B
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
PS2, USB
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
32
Number Of Timers
1
Operating Supply Voltage
4 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
CY3654, CY3654-P02
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-1852

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USB Serial Interface Engine (SIE)
The SIE allows the microcontroller to communicate with the USB
host. The SIE simplifies the interface between the
microcontroller and USB by incorporating hardware that handles
the following USB bus activity independently of the
microcontroller:
Firmware is required to handle the rest of the USB interface with
the following tasks:
USB Enumeration
The enumeration sequence is shown below:
Table 17. USB Status and Control Register
Document #: 38-08027 Rev. *E
1. The host computer sends a Setup packet followed by a Data
2. The USB Controller decodes the request and retrieves its
3. The host computer performs a control read sequence and the
4. After receiving the descriptor, the host computer sends a
5. The USB Controller stores the new address in its USB Device
Bit stuffing/unstuffing
Checksum generation/checking
ACK/NAK
Token type identification
Address checking
Coordinate enumeration by responding to set-up packets
Fill and empty the FIFOs
Suspend/Resume coordination
Verify and select Data toggle values
packet to USB address 0 requesting the Device descriptor.
Device descriptor from the program memory space.
USB Controller responds by sending the Device descriptor
over the USB bus.
Setup packet followed by a Data packet to address 0
assigning a new USB address to the device.
Address Register after the no-data control sequence is
complete.
Reserved
7
Addr:0x1F
Reserved
6
D+
R
5
USB Status and Control Register
D–
R
4
Bus Activity
PS/2 Operation
PS/2 operation is possible with the CY7C63413C/513C/613C
series through the use of firmware and several operating modes.
The first enabling feature:
Bits 5 and 4 of the Upstream Status and Control register are
directly connected to the D+ and D USB pins of the
CY7C63413C/513C/613C. These pins constantly monitor the
levels of these signals with CMOS input thresholds. Firmware
can poll and decode these signals as PS/2 clock and data.
Bits [2:0] defaults to ‘000’ at reset which allows the USB SIE to
control output on D+ and D. Firmware can override the SIE and
directly control the state of these pins via these 3 control bits.
Since PS/2 is an open drain signaling protocol, these modes
allow all 4 PS/2 states to be generated on the D+ and D pins
USB Port Status and Control
USB status and control is regulated by the USB Status and
Control Register located at I/O address 0x1F as shown in
Figure
written to zero. All bits in the register are cleared during reset.
6. The host sends a request for the Device descriptor using the
7. The USB Controller decodes the request and retrieves the
8. The host performs a control read sequence and the USB
9. The host generates control reads to the USB Controller to
10.The USB Controller retrieves the descriptors from its program
1. USB Bus reset on D+ and D is an interrupt that can be dis-
2. USB traffic can be disabled via bit 7 of the USB register;
3. D+ and D can be monitored and driven via firmware as
R/W
3
new USB address.
Device descriptor from the program memory.
Controller responds by sending its Device descriptor over the
USB bus.
request the Configuration and Report descriptors.
space and returns the data to the host over the USB.
abled;
independent port bits.
17. This is a read/write register. All reserved bits must be
Control
Bit 2
R/W
2
Control
Bit 1
R/W
1
CY7C63413C
CY7C63513C
CY7C63613C
Control
Bit 0
R/W
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