MB86R01PB-GSE1 Fujitsu Semiconductor America Inc, MB86R01PB-GSE1 Datasheet - Page 8

• Manufacturer Part Number: MB86R01PB-GSE1
• Description: IC SOC GRAPHIC CONTRLR 484BGA
• Manufacturer: Fujitsu Semiconductor America Inc

Specifications of MB86R01PB-GSE1

• Applications: Graphics Controller
• Core Processor: ARM9
• Program Memory Type: External Program Memory
• Controller Series: Jade
• Ram Size: 64K x 8
• Interface: ADC, ATA, CAN, EBI/EMI, I²C, I²S, Media LB, PWM, SD Card, UART/USART, USB
• Number Of I /o: 24
• Voltage - Supply: 1.1 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 484-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1110

FUJITSU MICROELECTRONICS
PROPRIETARY AND CONFIDENTIAL
MB86R01 DATA SHEET
3.
Figure 3-1 shows block diagram of MB86R01.
CPU core
This is CPU core block of ARM926EJ-S which is connected to each I/O through AHB bus in LSI.
Instruction (I)/Data (D) function as a separate bus master for Harvard architecture.
GDC_TOP
This is MB86296 compatible GDC which has 2 functions: AHB slave function writes required display list
for drawing to GDC with having CPU or DMA controller as master, and AXI master function reads display
list arranged in DDR2 memory with having GDC as master.
AXI bus
This bus bridges main memory and internal resource. Following four bus masters are connected.
• I2S is addable up to 3ch
• The number of UART channel is extensible up to 6ch
• The data width in the external bus interface is extensible to 32 bit
• AHB1: Each bus master of AHB bus such as CPU and DMA controller
• HBUS: HOST IF on GDC
• DRAW & GEO: Draw (2D/3D drawing) and GEO (geometry engine) on GDC
• MBUS: DISP (display controller) and CAP (Video capture) on GDC
Block diagram
S1-05
S2-00
External
BUS I/F
CCPB
IRC
×2
IRC
S1-00
Chip_JTAG
SRAM
32KB
EXTIRC
4ch
S1-08
JTAG_SEL
Function
USB2.0
DMAC
SRAM
32KB
M1-5
CRG
D-Cache
I-Cache
S1-01
16KB
16KB
M1-2
Function
Wrapper
USB2.0
DMAC
UART
8ch
UART
×2
JTAG IF
S2-03
×4
S1-02
PHY
GPIO
24ch
I
M1-0
M1-8
Figure 3-1 Block diagram of MB86R01
D
USB2.0
Wrapper
Host
M1-1
RBC
S2-02
M1-4
SDMC
Timer
32bit
2ch
S2-01
BOOT
32KB
ROM
S1-04
ETM9CSSingle
DMAC
IDE66
M1-6
2
IDE66
D-TCM
I-TCM
16KB
16KB
×2
S1-07
I2C
I2S_0
×2
I2C
S1-13
CAN
×2
I2S_1
CAN
×2
S1-14
S1-06
UART
×2
I2S_2
PWM
×2
S1-10
ADC
×2
ADC
S2-04
×4
AHB2AXI
S1-15
S1-03
M2-0
HOST IF
S1-12
DDR2 Controller
HBUS2AXI
PWM
2ch
S1-11
MediaLB
M1-7
SPI
×1
MBUS2AXI
DISP
DISP
CAP
CAP
DRAW & GEO
CCNT
S1-09
MBUS2AXI
UART
UART
×2
×4
Slave No.
Master No.