AT94K05AL-25AQU Atmel, AT94K05AL-25AQU Datasheet - Page 201
AT94K05AL-25AQU
Manufacturer Part Number
AT94K05AL-25AQU
Description
IC FPSLIC 5K GATE 25MHZ 100-TQFP
Manufacturer
Atmel
Series
FPSLIC®r
Datasheet
1.AT94K05AL-25AJI.pdf
(204 pages)
Specifications of AT94K05AL-25AQU
Core Type
8-bit AVR
Speed
25MHz
Interface
I²C, UART
Program Sram Bytes
4K-16K
Fpga Sram
2kb
Data Sram Bytes
4K ~ 16K
Fpga Core Cells
256
Fpga Gates
5K
Fpga Registers
436
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
For Use With
ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Table of Contents
1138I–FPSLI–1/08
1
2
3
4
Description ............................................................................................... 2
FPGA Core ................................................................................................ 4
FPGA/AVR Interface and System Control ........................................... 21
AVR Core and Peripherals .................................................................... 34
2.1Fast, Flexible and Efficient SRAM .............................................................................4
2.2Fast, Efficient Array and Vector Multipliers ................................................................4
2.3Cache Logic Design ..................................................................................................4
2.4Automatic Component Generators ............................................................................5
2.5The Symmetrical Array ..............................................................................................5
2.6The Busing Network ..................................................................................................6
2.7Cell Connections .......................................................................................................8
2.8The Cell .....................................................................................................................8
2.9RAM ........................................................................................................................10
2.10Clocking and Set/Reset .........................................................................................14
3.1FPGA/AVR Interface – Memory-mapped Peripherals .............................................21
3.2Program and Data SRAM ........................................................................................22
3.3Data SRAM Access by FPGA – FPGAFrame Mode ...............................................24
3.4SRAM Access by FPGA/AVR .................................................................................24
3.5AVR Cache Mode ....................................................................................................29
3.6Resets .....................................................................................................................29
3.7System Control ........................................................................................................30
4.1Instruction Set Nomenclature (Summary) ...............................................................35
4.2Complete Instruction Set Summary .........................................................................36
4.3Pin Descriptions ......................................................................................................40
4.4Clock Options ..........................................................................................................41
4.5Architectural Overview ............................................................................................43
4.6General-purpose Register File ................................................................................44
4.7X-register, Y-register and Z-register ........................................................................45
4.8ALU – Arithmetic Logic Unit ....................................................................................45
4.9Multiplier Unit ...........................................................................................................45
4.10SRAM Data Memory .............................................................................................45
4.11Memory-mapped I/O .............................................................................................48
4.12Software Control of System Configuration ............................................................52
AT94KAL Series FPSLIC
i
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