AT94K05AL-25AQU Atmel, AT94K05AL-25AQU Datasheet - Page 15
AT94K05AL-25AQU
Manufacturer Part Number
AT94K05AL-25AQU
Description
IC FPSLIC 5K GATE 25MHZ 100-TQFP
Manufacturer
Atmel
Series
FPSLIC®r
Datasheet
1.AT94K05AL-25AJI.pdf
(204 pages)
Specifications of AT94K05AL-25AQU
Core Type
8-bit AVR
Speed
25MHz
Interface
I²C, UART
Program Sram Bytes
4K-16K
Fpga Sram
2kb
Data Sram Bytes
4K ~ 16K
Fpga Core Cells
256
Fpga Gates
5K
Fpga Registers
436
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
For Use With
ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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1138I–FPSLI–1/08
The FPGA clocks from the AVR are effected differently in the various sleep modes of the AVR,
see
The source clock into the FPGA GCK5 and GCK6 will determine what happens during the vari-
ous power-down modes of the AVR.
If the XTAL clock input is used as an FPGA clock (GCK5 or GCK6) in Idle mode, it will still be
running. In Power-down/save mode the XTAL clock input will be off.
If the TOSC clock input is used as an FPGA clock (GCK6) in Idle mode, it will still be running in
Power-save mode but will be off in Power-down mode.
If the Watchdog Timer is used as an FPGA clock (GCK6) and was enabled in the AVR, it will be
running in all sleep modes.
Table 2-1.
Mode
Idle
Power-save
Power-down
Table
2-1.
Clock Activity in Various Modes
Clock Source
XTAL
TOSC
WDT
XTAL
TOSC
WDT
XTAL
TOSC
WDT
GCK5
Active
Not Available
Not Available
Inactive
Not Available
Not Available
Inactive
Not Available
Not Available
AT94KAL Series FPSLIC
GCK6
Active
Active
Active
Inactive
Active
Active
Inactive
Inactive
Active
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