AT94K10AL-25AQC Atmel, AT94K10AL-25AQC Datasheet - Page 97
AT94K10AL-25AQC
Manufacturer Part Number
AT94K10AL-25AQC
Description
IC FPSLIC 10K GATE 25MHZ 100TQFP
Manufacturer
Atmel
Series
FPSLIC®r
Specifications of AT94K10AL-25AQC
Core Type
8-bit AVR
Speed
25MHz
Interface
I²C, UART
Program Sram Bytes
20K-32K
Fpga Sram
4kb
Data Sram Bytes
4K ~ 16K
Fpga Core Cells
576
Fpga Gates
10K
Fpga Registers
846
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
100-TQFP, 100-VQFP
For Use With
ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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1138I–FPSLI–1/08
Figure 4-29. Effects of Unsynchronized OCR Latching in Up/Down Mode
Note:
Figure 4-30. Effects of Unsynchronized OCR Latching in Overflow Mode.
Note:
During the time between the write and the latch operation, a read from the Output Compare
Registers will read the contents of the temporary location. This means that the most recently
written value always will read out of OCR0 and OCR2.
When the Output Compare Register contains $00 or $FF, and the up/down PWM mode is
selected, the output PE1(OC0/PWM0)/PE3(OC2/PWM2) is updated to Low or High on the next
compare match according to the settings of COMn1/COMn0. This is shown in
overflow PWM mode, the output PE1(OC0/PWM0)/PE3(OC2/PWM2) is held Low or High only
when the Output Compare Register contains $FF.
Compare Value Changes
1. n = 0 or 2
1. n = 0 or 2
Compare Value Changes
Unsynchronized OCn
Synchronized OCn
Synchronized OCn
Unsynchronized OCn
(1)
(1)
(1)
Latch
Latch
Latch
(1)
Latch
AT94KAL Series FPSLIC
Compare Value Changes
Glitch
Compare Value Changes
Glitch
Counter Value
Compare Value
PWM Output OCn
Counter Value
Compare Value
PWM Output OCn
Counter Value
Compare Value
PWM Output OCn
Counter Value
Compare Value
PWM Output OCn
Table
4-16. In
(1)
(1)
(1)
(1)
97
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