AT94K10AL-25AQC Atmel, AT94K10AL-25AQC Datasheet - Page 140
AT94K10AL-25AQC
Manufacturer Part Number
AT94K10AL-25AQC
Description
IC FPSLIC 10K GATE 25MHZ 100TQFP
Manufacturer
Atmel
Series
FPSLIC®r
Specifications of AT94K10AL-25AQC
Core Type
8-bit AVR
Speed
25MHz
Interface
I²C, UART
Program Sram Bytes
20K-32K
Fpga Sram
4kb
Data Sram Bytes
4K ~ 16K
Fpga Core Cells
576
Fpga Gates
10K
Fpga Registers
846
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
100-TQFP, 100-VQFP
For Use With
ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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2-wire Serial Interface (Byte Oriented)
AT94KAL Series FPSLIC
The 2-wire Serial Bus is a bi-directional two-wire serial communication standard. It is designed
primarily for simple but efficient integrated circuit (IC) control. The system is comprised of two
lines, SCL (Serial Clock) and SDA (Serial Data) that carry information between the ICs con-
nected to them. Various communication configurations can be designed using this bus.
Figure 4-45
can be Master or Slave.
Figure 4-45. 2-wire Serial Bus Configuration
The 2-wire Serial Interface provides a serial interface that meets the 2-wire Serial Bus specifica-
tion and supports Master/Slave and Transmitter/Receiver operation at up to 400 kHz bus clock
rate. The 2-wire Serial Interface has hardware support for the 7-bit addressing, but is easily
extended to 10-bit addressing format in software. When operating in 2-wire Serial mode, i.e.,
when TWEN is set, a glitch filter is enabled for the input signals from the pins SCL and SDA, and
the output from these pins are slew-rate controlled. The 2-wire Serial Interface is byte oriented.
The operation of the serial 2-wire Serial Bus is shown as a pulse diagram in
ing the START and STOP conditions and generation of ACK signal by the bus receiver.
Figure 4-46. 2-wire Serial Bus Timing Diagram
The block diagram of the 2-wire Serial Bus interface is shown in
SDA
SCL
CONDITION
START
shows a typical 2-wire Serial Bus configuration. Any device connected to the bus
MSB
Device 1
1
2
Device 2
7
R/W
BIT
8
Device 3
ACK
9
FROM RECEIVER
ACKNOWLEDGE
.......
1
2
Device n
Figure
8
REPEATED START CONDITION
R1
4-47.
ACK
9
R2
Figure
STOP CONDITION
1138I–FPSLI–1/08
4-46, includ-
V
SCL
SDA
CC
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