AT94K05AL-25AJI Atmel, AT94K05AL-25AJI Datasheet - Page 72
AT94K05AL-25AJI
Manufacturer Part Number
AT94K05AL-25AJI
Description
IC FPSLIC 5K GATE 25MHZ 84PLCC
Manufacturer
Atmel
Series
FPSLIC®r
Specifications of AT94K05AL-25AJI
Core Type
8-bit AVR
Speed
25MHz
Interface
I²C, UART
Program Sram Bytes
4K-16K
Fpga Sram
2kb
Data Sram Bytes
4K ~ 16K
Fpga Core Cells
256
Fpga Gates
5K
Fpga Registers
436
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
84-PLCC
For Use With
ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Figure 4-16. Block Diagram
72
TDI
TDO
TCK
TMS
AT94KAL Series FPSLIC
CONTROLLER
M
U
X
TAP
JTAG INSTRUCTION
DEVICE BOUNDARY
BREAKPOINT
SCAN CHAIN
SCAN CHAIN
AVR RESET
REGISTER
DEVICE ID
REGISTER
REGISTER
When the JTAGEN bit is unprogrammed, these four TAP pins revert to normal operation. When
programmed, the input TAP signals are internally pulled High and the JTAG is enabled for
Boundary-Scan. System Designer sets this bit by default.
For the On-Chip Debug system, in addition the RESET pin is monitored by the debugger to be
able to detect external reset sources. The debugger can also pull the RESET pin Low to reset
the whole system, assuming only open collectors on reset line are used in the application.
BYPASS
ADDRESS
DECODER
RESET CONTROL
PROGRAM/DATA
AND CONTROL
BREAKPOINT
OCD STATUS
SCAN CHAIN
SCAN CHAIN
FPGA-SRAM
FPGA-AVR
SRAM
UNIT
UNIT
M
U
X
2-wire Serial
PORT E
INTERNAL
FLOW CONTROL
CHAIN
SCAN
UNIT
AVR BOUNDARY-SCAN CHAIN
PC
Instruction
COMMUNICATION
OCD / AVR CORE
PERIPHERAL
INTERFACE
AVR CPU
DIGITAL
UNITS
1138I–FPSLI–1/08
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