AT94K05AL-25AJI Atmel, AT94K05AL-25AJI Datasheet - Page 35
AT94K05AL-25AJI
Manufacturer Part Number
AT94K05AL-25AJI
Description
IC FPSLIC 5K GATE 25MHZ 84PLCC
Manufacturer
Atmel
Series
FPSLIC®r
Specifications of AT94K05AL-25AJI
Core Type
8-bit AVR
Speed
25MHz
Interface
I²C, UART
Program Sram Bytes
4K-16K
Fpga Sram
2kb
Data Sram Bytes
4K ~ 16K
Fpga Core Cells
256
Fpga Gates
5K
Fpga Registers
436
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
84-PLCC
For Use With
ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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4.1
4.1.1
4.1.2
4.1.3
4.1.3.1
4.1.3.2
1138I–FPSLI–1/08
Instruction Set Nomenclature (Summary)
Status Register (SREG)
Registers and Operands
I/O Registers
Stack
Flags
The complete “AVR Instruction Set” document is available on the Atmel web site, at
http://www.atmel.com/atmel/acrobat/doc0856.pdf.
SREG:
C:
Z:
N:
V:
S:
H:
T:
I:
Rd:
Rr:
R:
K:
k:
b:
s:
X,Y,Z:
A:
q:
STACK:
SP:
⇔:
0:
1:
-:
The instructions EIJMP, EICALL, ELPM, GPM, ESPM (from the megaAVR Instruction Set) are
not supported in the FPSLIC device.
Status register
Carry flag in status register
Zero flag in status register
Negative flag in status register
Two’s complement overflow indicator
N ⊕ V, For signed tests
Half-carry flag in the status register
Transfer bit used by BLD and BST instructions
Global interrupt enable/disable flag
Destination (and source) register in the register file
Source register in the register file
Result after instruction is executed
Constant data
Constant address
Bit in the register file or I/O register (0
Bit in the status register (0
Indirect address register (X = R27:R26, Y = R29:R28 and Z = R31:R30)
I/O location address
Displacement for direct addressing (0
Stack for return address and pushed registers
Stack Pointer to STACK
Flag affected by instruction
Flag cleared by instruction
Flag set by instruction
Flag not affected by instruction
≤
s
≤
2)
AT94KAL Series FPSLIC
≤
≤
q
b
≤
≤
63)
7)
35
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