XC5VFX30T-1FF665CES Xilinx Inc, XC5VFX30T-1FF665CES Datasheet - Page 66
XC5VFX30T-1FF665CES
Manufacturer Part Number
XC5VFX30T-1FF665CES
Description
IC FPGA VIRTEX5FX 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 FXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VFX30T-1FF665CES
Number Of Logic Elements/cells
32768
Number Of Labs/clbs
2560
Total Ram Bits
2506752
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS Compliant
Number Of Gates
-
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Part Number:
XC5VFX30T-1FF665CES
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Quantity:
10 000
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Chapter 2: Clock Management Technology
X-Ref Target - Figure 2-4
66
Source
CLK
IBUFG
System-Synchronous
This delay element allows adjustment of the effective clock delay between the clock source
and CLK0 to guarantee non-positive hold times of IOB input flip-flop in the device.
Adding more delay to the DCM feedback path decreases the effective delay of the actual
clock path from the FPGA clock input pin to the clock input of any flip-flop. Decreasing the
clock delay increases the setup time represented in the input flip-flop, and reduces any
positive hold times required. The clock path delay includes the delay through the IBUFG,
route, DCM, BUFG, and clock-tree to the destination flip-flop. If the feedback delay equals
the clock-path delay, the effective clock-path delay is zero.
System-Synchronous Setting (Default)
By default, the feedback delay is set to system-synchronous mode. The primary timing
requirements for a system-synchronous system are non-positive hold times (or minimally
positive hold times) and minimal clock-to-out and setup times. Faster clock-to-out and
setup times allow shorter system clock periods. Ideally, the purpose of a DLL is to zero-out
the clock delay to produce faster clock-to-out and non-positive hold times. The system-
synchronous setting (default) for DESKEW_ADJUST configures the feedback delay
element to guarantee non-positive hold times for all input IOB registers. The exact delay
number added to the feedback path is device size dependent. This is determined by
characterization. In the timing report, this is included as timing reduction to input clock
path represented by the T
includes tap delays in the default setting (red line). The pin-to-pin timing parameters (with
DCM) on the Virtex-5 FPGA Data Sheet reflects the setup/hold and clock-to-out times when
the DCM is in system-synchronous mode.
In some situations, the DCM does not add this extra feedback delay, and the
DESKEW_ADJUST parameter has no effect. BitGen selects the appropriate DCM Tap
settings. These situations include:
Default Setting
Figure 2-4: DCM and Feedback Tap-Delay Elements
DCM
Feedback Tap Delays
…
Setting (Delay set to zero)
CLKIN
CLKFB
Source-Synchronous
DCMINO
www.xilinx.com
CLK0
Data Input
parameter. As shown in
Regulator
V
Power
DCM
CCINT
V
CCO
Figure
D
FF
Q
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
2-4, the feedback path
ug190_2_04_042506
Into the
V
FPGA
CCAUX
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