XC5VFX30T-1FF665CES Xilinx Inc, XC5VFX30T-1FF665CES Datasheet - Page 375
![IC FPGA VIRTEX5FX 30K 665FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VFX30T-1FF665CES
Manufacturer Part Number
XC5VFX30T-1FF665CES
Description
IC FPGA VIRTEX5FX 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 FXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VFX30T-1FF665CES
Number Of Logic Elements/cells
32768
Number Of Labs/clbs
2560
Total Ram Bits
2506752
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS Compliant
Number Of Gates
-
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Part Number:
XC5VFX30T-1FF665CES
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
OSERDES Clocking Methods
OSERDES Width Expansion
DATA_WIDTH Attribute
SERDES_MODE Attribute
TRISTATE_WIDTH Attribute
The DATA_WIDTH attribute defines the parallel data input width of the parallel-to-serial
converter. The possible values for this attribute depend on the DATA_RATE_OQ attribute.
When DATA_RATE_OQ is set to SDR, the possible values for the DATA_WIDTH attribute
are 2, 3, 4, 5, 6, 7, and 8. When DATA_RATE_OQ is set to DDR, the possible values for the
DATA_WIDTH attribute are 4, 6, 8, and 10.
When the DATA_WIDTH is set to widths larger than six, a pair of OSERDES must be
configured into a master-slave configuration. See
The SERDES_MODE attribute defines whether the OSERDES module is a master or slave
when using width expansion. The possible values are MASTER and SLAVE. The default
value is MASTER. See
The TRISTATE_WIDTH attribute defines the parallel 3-state input width of the 3-state
control parallel-to-serial converter. The possible values for this attribute depend on the
DATA_RATE_TQ attribute. When DATA_RATE_TQ is set to SDR or BUF, the
TRISTATE_WIDTH attribute can only be set to 1. When DATA_RATE_TQ is set to DDR,
the possible values for the TRISTATE_WIDTH attribute is 4.
TRISTATE_WIDTH cannot be set to widths larger than 4. When a DATA_WIDTH is larger
than four, set the TRISTATE_WIDTH to 1.
The phase relationship of CLK and CLKDIV is important in the parallel-to-serial
conversion process. CLK and CLKDIV are (ideally) phase-aligned within a tolerance.
There are several clocking arrangements within the FPGA to help the design meet the
phase relationship requirements of CLK and CLKDIV. The only valid clocking
arrangements for the OSERDES are:
•
•
•
Two OSERDES modules are used to build a parallel-to-serial converter larger than 6:1. In
every I/O tile there are two OSERDES modules; one master and one slave. By connecting
the SHIFTIN ports of the master OSERDES to the SHIFTOUT ports of the slave OSERDES,
the parallel-to-serial converter can be expanded to up to 10:1(DDR) and 8:1 (SDR). For a
differential output, the master OSERDES must be on the positive side of the differential
output pair. When the output is not differential, the output buffer associated with the slave
OSERDES is not available and can not be used.
When using the OSERDES with width expansion, complementary single-ended standards
(e.g., DIFF_HSTL and DIFF_SSTL) cannot be used. This is because both OLOGIC blocks in
an I/O tile are used by the complementary single-ended standards to transmit both legs of
the signal, leaving no OLOGIC blocks available for width expansion.
CLK driven by BUFIO, CLKDIV driven by BUFR
CLK driven by DCM, CLKDIV driven by the CLKDV output of the same DCM
CLK driven by PLL, CLKDIV driven by CLKOUT[0:5] of same PLL
OSERDES Width
www.xilinx.com
Output Parallel-to-Serial Logic Resources (OSERDES)
Expansion.
OSERDES Width
Expansion.
375
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