XC5VFX30T-1FF665CES Xilinx Inc, XC5VFX30T-1FF665CES Datasheet - Page 361
![IC FPGA VIRTEX5FX 30K 665FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VFX30T-1FF665CES
Manufacturer Part Number
XC5VFX30T-1FF665CES
Description
IC FPGA VIRTEX5FX 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 FXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VFX30T-1FF665CES
Number Of Logic Elements/cells
32768
Number Of Labs/clbs
2560
Total Ram Bits
2506752
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS Compliant
Number Of Gates
-
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Part Number:
XC5VFX30T-1FF665CES
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Xilinx Inc
Quantity:
10 000
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ISERDES Width Expansion
Memory Interface Type
The only valid clocking arrangements for the ISERDES_NODELAY block using the
memory interface type are:
•
•
•
The clocking arrangement using BUFIO and BUFR is shown in
CLKDIV inputs must be nominally phase-aligned. For example, if CLK and CLKDIV in
Figure 8-6
clocking arrangement is a legal BUFIO/BUFR configuration, the clocks would still be out
of phase. No phase relationship between CLK and OCLK is expected. Calibration must be
performed for reliable data transfer from CLK to OCLK domain.
Strobe-Based Memory Interfaces - OCLK
between CLK and OCLK.
X-Ref Target - Figure 8-6
Two ISERDES modules are used to build a serial-to-parallel converter larger than 1:6. In
every I/O tile there are two ISERDES modules; one master and one slave. By connecting
the SHIFTOUT ports of the master ISERDES to the SHIFTIN ports of the slave ISERDES the
serial-to-parallel converter can be expanded to up to 1:10 (DDR) and 1:8 (SDR).
Figure 8-7
master and slave ISERDES modules. Ports Q3 - Q6 are used for the last four bits of the
parallel interface on the slave ISERDES.
For a differential input, the master ISERDES must be on the positive side of the differential
input pair. When the input is not differential, the input buffer associated with the slave
ISERDES is not available and can not be used.
CLK driven by BUFIO or BUFG
OCLK driven by DCM and CLKDIV driven by CLKDV output of same DCM
OCLK driven by PLL and CLKDIV driven by CLKOUT[0:5] of same PLL
Clock
Input
were inverted by the designer at the ISERDES inputs, then although the
illustrates a block diagram of a 1:10 DDR serial-to-parallel converter using the
Figure 8-6: Clocking Arrangement Using BUFIO and BUFR
www.xilinx.com
BUFR ( ÷ X)
BUFIO
Input Serial-to-Parallel Logic Resources (ISERDES)
gives further information about transferring data
ISERDES_NODELAY
CLK
CLKDIV
Figure
High-Speed Clock for
8-6. The CLK and
UG190_8_06_110807
361
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