XC4036XL-09BG352C Xilinx Inc, XC4036XL-09BG352C Datasheet - Page 8

• Manufacturer Part Number: XC4036XL-09BG352C
• Description: IC FPGA C-TEMP 3.3V 352-MBGA
• Manufacturer: Xilinx Inc
• Series: XC4000E/Xr

Specifications of XC4036XL-09BG352C

• Number Of Logic Elements/cells: 3078
• Number Of Labs/clbs: 1296
• Total Ram Bits: 41472
• Number Of I /o: 288
• Number Of Gates: 36000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 352-LBGA, Metal
• Case: BGA
• Dc: 00+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

clocked in on each consecutive rising CCLK edge
(Figure
Pseudo Daisy Chain
As illustrated in Figures 5 and 6, multiple devices with dif-
ferent configurations can be configured in a pseudo daisy
chain provided that all of the devices are in Express mode.
A single combined byte-wide data stream is used to config-
ure the chain of Express mode devices. CCLK pins are tied
together and D0-D7 pins are tied together as a data buss
for all devices along the chain. A status signal is passed
from DOUT of each device to the CS1 input of the device
which follows it in the chain. Frame data is accepted only
when CS1 is High and the device’s configuration memory is
not already full. The lead device in the chain has its CS1
input tied High (or floating, since there is an internal pullup).
The status pin DOUT is initially High for all devices in the
chain until the data stream header of seven bytes is loaded.
This allows header data to be loaded into all devices in the
chain simultaneously. After the header is loaded in all
devices, their DOUT pins are pulled Low disabling configu-
ration of all devices in the chain except the first device. As
each device in the chain is filled, its DOUT goes High driv-
ing High the CS1 input of the next device, thereby enabling
configuration of the next device in the pseudo daisy chain.
The requirement that all DONE pins in a daisy chain be
wired together applies only to Express mode, and only if all
devices in the chain are to become active simultaneously.
All 4000XLA/XV devices in Express mode are synchro-
nized to the DONE pin. User I/O for each device becomes
active after the DONE pin for that device goes High (The
exact timing is determined by BitGen options.)
Since the DONE pin is open-drain and does not drive a
High value, tying the DONE pins of all devices together pre-
vents all devices in the chain from going High until the last
device in the chain has completed its configuration cycle. If
the DONE pin of a device is left unconnected, the device
6-164
6).
R
XC4000XLA/XV Field Programmable Gate Arrays
becomes active as soon as that device has been config-
ured.
Table 7: Pin Functions During Configuration
(4000XLA/XV Express mode only)
Because only XC4000XLA/XV, SpartanXL, and XC5200
devices support Express mode, only these devices can be
used to form an Express mode pseudo daisy chain.
Notes
CONFIGURATION MODE
DS015 (v1.3) October 18, 1999 - Product Specification
EXPRESS MODE
PROGRAM (I)
<M2:M1:M0>
M1(HIGH) (I)
M2(LOW) (I)
M0(LOW) (I)
HDC (HIGH)
LDC (LOW)
1. A shaded table cell represents the internal
2. (I) represents an input; (O) represents an
3. INIT is an open-drain output during
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
CCLK (I)
<0:1:0>
DONE
DOUT
pull-up used before and during
configuration.
output.
configuration.
TMS
TDO
INIT
TCK
CS1
TDI
PIN FUNCTION
OPERATION
PROGRAM
SGCK4-I/O
CCLK (I)
TMS-I/O
TDO-(O)
TCK-I/O
TDI-I/O
USER
DONE
M2
M1
M0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O