XC4036XL-09BG352C Xilinx Inc, XC4036XL-09BG352C Datasheet
XC4036XL-09BG352C
Specifications of XC4036XL-09BG352C
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XC4036XL-09BG352C Summary of contents
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... Table 1: XC4000XLA Series Field Programmable Gate Arrays * Max Logic Logic Gates Device Cells (No RAM) XC4013XLA 1,368 13,000 XC4020XLA 1,862 20,000 XC4028XLA 2,432 28,000 XC4036XLA 3,078 36,000 XC4044XLA 3,800 44,000 XC4052XLA 4,598 52,000 XC4062XLA 5,472 62,000 XC4085XLA 7,448 85,000 XC40110XV 9,728 110,000 ...
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R General Description XC4000 Series high-performance, high-capacity Field Pro- grammable Gate Arrays (FPGAs) provide the benefits of custom CMOS VLSI, while avoiding the initial cost, long development cycle, and inherent risk of a conventional masked gate array. The result of ...
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R Three-State Register XC4000XLA/XV devices incorporate an optional register controlling the three-state enable in the IOBs.The use of the three-state control register can significantly improve output enable and disable time. FastCLK Clock Buffers The XLA/XV devices incorporate FastCLK clock buffers. ...
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R Using Fast I/O CLKS There are several issues associated with implementing fast I/O clocks by using multiple FastCLK and BUFGE clock buffers for I/O transfers and a BUFGLS clock buffer for internal logic. Reduced Clock to Out Period - ...
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... Family Codes = 01 for XLA for SpartanXL for Virtex for XV. Xilinx company code = 49 (hex) Table 4: IDCODEs assigned to XC4000XLA/XV FPGAs FPGA XC4013XLA 0x00218093 XC4020XLA 0x0021c093 XC4028XLA 0x00220093 XC4036XLA 0x00224093 XC4044XLA 0x00228093 XC4052XLA 0x0022c093 XC4062XLA 0x00230093 XC4085XLA 0x00238093 XC40110XV 0x00e40093 XC40150XV 0x00e48093 ...
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R be connected to a 2.5V power supply. The differences between the XL and XV packages are detailed below: PG559 - XLA and XL devices in the PG599 package have 56 VCC pins.The XC4000XV devices allocate 16 of these I/O ...
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R I/O Signalling Standards XLA and XV devices are compatible with TTL, LVTTL, PCI 3V, PCI 5V and LVCMOS signalling. The various standards are illustrated in Table 6 and the signaling environment is illustrated in Figure 4. VCC Clamping XLA/XV ...
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R clocked in on each consecutive rising CCLK edge (Figure 6). Pseudo Daisy Chain As illustrated in Figures 5 and 6, multiple devices with dif- ferent configurations can be configured in a pseudo daisy chain provided that all of the ...
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R M0 CS1 8 D0-D7 DATA BUS VCC 4000XLA/XV 4.7K PROGRAM PROGRAM INIT INIT CCLK CCLK Figure 5: Express Mode Circuit Diagram Table 8: Express Mode Programming Switching Characteristic Description INIT (High) setup time setup time D0 ...
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R CCLK INIT D0-D7 DOUT CS1 First FPGA CS1 Second FPGA CS1 all downstream FPGAs Byte A is first frame byte for first FPGA Byte B is last frame byte for first FPGA Byte C is first ...
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... Table 11: User I/O Pins Available by Device and Package Max I/O Device 192 129 XC4013XLA 224 129 XC4020XLA 256 129 XC4028XLA 288 129 XC4036XLA 320 129 XC4044XLA 352 129 XC4052XLA 384 129 XC4062XLA 448 129 XC4085XLA 448 XC40110XV 448 ...
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... Xilinx W the specifications. Table 12: Component Availability Chart for XC4000XLA FPGAs PINS 84 100 100 144 TYPE CODE -09 XC4013XLA -08 -07 -09 XC4020XLA -08 -07 -09 XC4028XLA -08 -07 -09 XC4036XLA -08 -07 -09 XC4044XLA -08 -07 -09 XC4052XLA -08 -07 -09 XC4062XLA -08 -07 -09 XC4085XLA -08 -07 1/25/ Commercial + ...
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R XV Family Table 13 show the current available package and speed grade combinations for the XC4000XV Series devices. Call your local sales office for the latest availability information, or see the Xilinx W revision of the specifications. Table 13: ...
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... Replaced Electrical Specification pages for XLA and XV families with separate updates and added URL link on placeholder page for electrical specifications/pinouts for WebLINX users. 10/18/99 (1.3) Deleted HQ304 package/XC4028XLA and XC4036XLA entries from Table 11, page 6-168. Changed do DS015. 6-170 XC4000XLA/XV Field Programmable Gate Arrays Description DS015 (v1.3) October 18, 1999 - Product Specifi ...