XC4036XL-09BG352C Xilinx Inc, XC4036XL-09BG352C Datasheet - Page 10

• Manufacturer Part Number: XC4036XL-09BG352C
• Description: IC FPGA C-TEMP 3.3V 352-MBGA
• Manufacturer: Xilinx Inc
• Series: XC4000E/Xr

Specifications of XC4036XL-09BG352C

• Number Of Logic Elements/cells: 3078
• Number Of Labs/clbs: 1296
• Total Ram Bits: 41472
• Number Of I /o: 288
• Number Of Gates: 36000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 352-LBGA, Metal
• Case: BGA
• Dc: 00+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Data Stream Format
The data stream (“bitstream”) format is identical for all
serial
4000XLA/XV Express mode. In Express mode, the device
becomes active when DONE goes High, therefore no
length count is required. Additionally, CRC error checking is
not supported in Express mode. The data stream format is
shown in
the left and D7 at the right.
The configuration data stream begins with two bytes of
eight ones each, a preamble code of one byte, followed by
three bytes of eight ones each, and finally an end-of-
header field check byte. This header of seven bytes is fol-
lowed by the actual configuration data in frames. The
length and number of frames depends on the device type.
Each frame begins with a start field and ends with an
end-of-frame field check byte. In all cases, additional
start-up bytes of data are required to provide six, or more,
clocks for the start-up sequence at the end of configuration.
Long daisy chains require additional startup bytes to shift
the last data through the chain. All startup bytes are
don’t-cares; these bytes are not included in bitstreams cre-
ated by the Xilinx software.
A selection of CRC or non-CRC error checking is allowed
by the bitstream generation software. The 4000XLA
Express mode only supports non-CRC error checking. The
non-CRC
end-of-frame field check byte for each frame. non-CRC
error checking tests for a designated end-of-frame field
check byte for each frame.
6-166
Figure 6: Express Mode Configuration Switching Waveforms
Note: CS1 must remain High throughout loading of the configuration data stream. In the pseudo daisy chain of
configuration
Table
data stream header is loaded into all devices simultaneously. Each device’s data frames are then loaded in turn when its
CS1 pin is driven High by the DOUT of the preceding device in the chain.
error
R
9. Express mode data is shown with D0 at
downstream
Second
CS1 all
FPGAs
checking
D0-D7
DOUT
FPGA
CCLK
FPGA
CS1
First
INIT
CS1
modes,
Byte A is first frame byte for first FPGA
Byte B is last frame byte for first FPGA
Byte C is first frame byte for second FPGA
1
T
tests
IC
but
2
for
T
different
BYTE
DC
0
a
BYTE
1
designated
BYTE
2
for
T
CD
Header
BYTE
3
3
the
XC4000XLA/XV Field Programmable Gate Arrays
BYTE
4
Header Loaded
BYTE
Table 9: 4000XLA/XV Express Mode Data Stream
Format
LEGEND:
Detection of an error results in the suspension of data load-
ing and the pulling down of the INIT pin. The user must
detect INIT and initialize a new configuration by pulsing the
PROGRAM pin Low or cycling VCC.
Fill Byte
Preamble Code
Fill Byte
End-of-Header
Field Check Byte
Start Field
Data Frame
End-of-Frame
Field Check Byte
Extend Write Cycle
Start-Up Bytes
5
Unshaded
Light
DS015 (v1.3) October 18, 1999 - Product Specification
BYTE
6
Data Type
BYTE
A
BYTE
B
Once per data stream
Once per data frame
BYTE
C
First FPGA Filled
99012600
FFFFh
11110010b
FFFFFFh
11010010b
11111110b
DATA(n-1:0)
11010010b
FFD2FFFFFFh
FFFFFFFFFFFFh
Figure
(4000XLA only)
Express Mode
(D0-D7)
5, the 7 byte