XCV812E-8FG900C Xilinx Inc, XCV812E-8FG900C Datasheet - Page 39

• Manufacturer Part Number: XCV812E-8FG900C
• Description: IC FPGA 1.8V C-TEMP 900-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV812E-8FG900C

• Number Of Logic Elements/cells: 21168
• Number Of Labs/clbs: 4704
• Total Ram Bits: 1146880
• Number Of I /o: 556
• Number Of Gates: 254016
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 900-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

As an added convenience, the BUFGP can be used to
instantiate a high fanout clock input. The BUFGP symbol
represents a combination of the LVTTL IBUFG and BUFG
symbols, such that the output of the BUFGP can connect
directly to the clock pins throughout the design.
Unlike previous architectures, the Virtex-E BUFGP symbol
can only be placed in a global clock pad location. The LOC
property can specify a location for the BUFGP.
OBUF
An OBUF must drive outputs through an external output
port. The generic output buffer (OBUF) symbol appears in
Figure
The extension to the base name defines which I/O standard
the OBUF uses. With no extension specified for the generic
OBUF symbol, the assumed standard is slew rate limited
LVTTL with 12 mA drive strength.
The LVTTL OBUF additionally can support one of two slew
rate modes to minimize bus transients. By default, the slew
rate for each output buffer is reduced to minimize power bus
transients when switching non-critical signals.
LVTTL output buffers have selectable drive strengths.
The format for LVTTL OBUF symbol names is as follows.
<slew_rate> is either F (Fast), or S (Slow) and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).
The following list details variations of the OBUF symbol.
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DS025-2 (v2.3) November 19, 2002
Figure 40: Virtex-E Output Buffer (OBUF) Symbol
OBUF_<slew_rate>_<drive_strength>
OBUF
OBUF_S_2
OBUF_S_4
OBUF_S_6
OBUF_S_8
OBUF_S_12
OBUF_S_16
OBUF_S_24
OBUF_F_2
OBUF_F_4
OBUF_F_6
OBUF_F_8
OBUF_F_12
OBUF_F_16
40.
R
I
OBUF
x133_04_111699
O
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
www.xilinx.com
1-800-255-7778
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The Virtex-E series supports eight banks for the HQ and PQ
packages. The CS packages support four V
OBUF placement restrictions require that within a given
V
voltage. Input buffers of any type and output buffers that do
not require V
Table 20
requirements. The LOC property can specify a location for
the OBUF.
Table 20:
OBUFT
The generic 3-state output buffer OBUFT, shown in
Figure
tional I/O.
The extension to the base name defines which I/O standard
OBUFT uses. With no extension specified for the generic
OBUFT symbol, the assumed standard is slew rate limited
LVTTL with 12 mA drive strength.
Rule 1
Rule 2
V
3.3
2.5
1.5
CCO
CCO
OBUF_F_24
OBUF_LVCMOS2
OBUF_PCI33_3
OBUF_PCI66_3
OBUF_GTL
OBUF_GTLP
OBUF_HSTL_I
OBUF_HSTL_III
OBUF_HSTL_IV
OBUF_SSTL3_I
OBUF_SSTL3_II
OBUF_SSTL2_I
OBUF_SSTL2_II
OBUF_CTT
OBUF_AGP
OBUF_LVCMOS18
OBUF_LVDS
OBUF_LVPECL
bank each OBUF share the same output source drive
41, typically implements 3-state outputs or bidirec-
summarizes the Virtex-E output compatibility
There are no placement restrictions for outputs
Only outputs with standards that share compatible
V
with standards that do not require a V
Compatible Standards
LVTTL, SSTL3_I, SSTL3_II, CTT, AGP, GTL,
GTL+, PCI33_3, PCI66_3
SSTL2_I, SSTL2_II, LVCMOS2, GTL, GTL+
HSTL_I, HSTL_III, HSTL_IV, GTL, GTL+
CCO
Output Standards Compatibility
Requirements
CCO
can be used within the same bank.
can be placed within any V
CCO
CCO
Module 2 of 4
CCO
banks.
bank.
.
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