XCV812E-7FG900C Xilinx Inc, XCV812E-7FG900C Datasheet
XCV812E-7FG900C
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R DS025-1 (v1.5) July 17, 2002 Features • Fast, Extended Block RAM, 1.8 V FPGA Family - 560 Kb and 1,120 Kb embedded block RAM - 130 MHz internal performance (four LUT levels) - PCI compliant 3.3 V, 32/64-bit, 33/66-MHz ...
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... Table 1: Virtex-E Extended Memory Field-Programmable Gate Array Family Members Device Logic Gates CLB Array XCV405E 129,600 XCV812E 254,016 Virtex-E Compared to Virtex Devices The Virtex-E family offers up to 43,200 logic cells in devices up to 30% faster than the Virtex family. I/O performance is increased to 622 Mb/s using Source ...
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... Number of Pins Package Type BG = Ball Grid Array FG = Fine Pitch Ball Grid Array Figure 1: Virtex Ordering Information www.xilinx.com 1-800-255-7778 Virtex-E -7 4.3 ns 6.3 ns 4.4 ns 5.1 ns 3.8 ns 5.5 ns 4.6 ns 3.5 ns 4.3 ns 5.9 ns XCV812E 404 556 = 0˚C to +85˚ −40˚C to +100˚C) J DS025_001_112000 Module ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Revision History The following table shows the revision history for this document. Date Version 03/23/00 1.0 Initial Xilinx release. 08/01/00 1.1 Accumulated edits and fixes. Upgrade to Preliminary. Preview -8 numbers ...
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R DS025-2 (v2.3) November 19, 2002 Architectural Description Virtex-E Array The Virtex-E user-programmable gate array (see comprises two major configurable elements: configurable logic blocks (CLBs) and input/output blocks (IOBs). • CLBs provide the functional elements for constructing logic. • IOBs ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 1: Supported I/O Standards I/O Output Input Standard V V CCO CCO LVTTL 3.3 3.3 LVCMOS2 2.5 2.5 LVCMOS18 1.8 1.8 SSTL3 I & II 3.3 N/A SSTL2 I & ...
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R IOBs, called banks. Consequently, restrictions exist about which I/O standards can be combined within a given bank. Eight I/O banks result from separating each edge of the FPGA into two banks, as shown in Figure multiple V pins, all ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays G4 G3 LUT LUT F5IN CLK CE In addition to the four ...
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... Table 4: Virtex-E Block SelectRAM Amounts Virtex-E Device # of Blocks Block SelectRAM Bits XCV405E 140 XCV812E 280 DS025-2 (v2.3) November 19, 2002 Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Arithmetic Logic Dedicated carry logic provides fast arithmetic carry capabil- ity for high-speed arithmetic functions. The Virtex-E CLB supports two separate carry chains, one per Slice ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays RAMB4_S#_S# WEA ENA DOA[#:0] RSTA CLKA ADDRA[#:0] DIA[#:0] WEB ENB RSTB DOB[#:0] CLKB ADDRB[#:0] DIB[#:0] Figure 6: Dual-Port Block SelectRAM Table 5 shows the depth and width aspect ratios for the ...
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R Dedicated Routing Some signal classes require dedicated routing resources to maximize performance. In the Virtex-E architecture, dedi- cated routing resources are provided for two signal classes. • Horizontal routing resources are provided for on-chip 3-state busses. Four partitionable bus ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays DLL provides four quadrature phases of the source clock, and can double the clock or divide the clock by 1. 16. The DLL also ...
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R Figure diagram of the Virtex-E Series boundary scan logic. It includes three bits of Data Register per IOB, the IEEE 1149.1 Test Access Port controller, and the Instruction Register with decodes. IOB IOB IOB IOB IOB ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 6: Boundary Scan Instructions Boundary-Scan Binary Command Code (4:0) EXTEST 00000 Enable boundary-scan EXTEST operation. SAMPLE/ 00001 Enable boundary-scan PRELOAD SAMPLE/PRELOAD operation. USER1 00010 Access user-defined register 1. USER2 00011 ...
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... Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 7: IDCODEs Assigned to Virtex-E FPGAs FPGA XCV405EM XCV812EM Note: Attempting to load an incorrect bitstream causes configuration to fail and can damage the device. Including Boundary Scan in a Design Since the boundary scan pins are dedicated, no special ele- ment needs to be added to the design unless an internal data register (USER1 or USER2) is desired ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays tions and the desired performance. Finally, the router inter- connects the blocks. The PAR algorithms support fully automatic implementation of most designs. For demanding applications, however, the user can exercise various ...
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... Table 9: Virtex-E Bitstream Lengths Device # of Configuration Bits XCV405E 3,430,400 XCV812E 6,519,648 Slave-Serial Mode In slave-serial mode, the FPGA receives configuration data in bit-serial form from a serial PROM or other source of serial configuration data. The serial bitstream must be set up at the DIN input pin a short time before each rising edge of an externally generated CCLK ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays VIRTEX-E PROGRAM DONE PROGRAM Figure 13: Master/Slave Serial Mode Circuit Diagram DIN CCLK DOUT (Output) Figure 14: Slave-Serial Mode Programming Switching Characteristics Master-Serial Mode In master-serial mode, the ...
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R The sequence of operations necessary to configure a Virtex-E FPGA serially appears in Figure Apply Power FPGA starts to clear configuration memory. Set PROGRAM = High FPGA makes a final clearing pass and releases INIT when finished. Release INIT ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays either asserted or de-asserted. Otherwise an abort is initiated, as described below. 2. Drive data onto D[7:0]. Note that to avoid contention, the data source should not be enabled while CS ...
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R Apply Power FPGA starts to clear configuration memory. PROGRAM from Low to High FPGA makes a final clearing pass and releases INIT when finished. Release INIT INIT? Set WRITE = Low Enter Data Source Set CS = Low Apply ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Configuration through the TAP uses the CFG_IN instruc- tion. This instruction allows data input on TDI to be con- verted into data packets for the internal configuration bus. The following steps ...
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R the internal storage elements to begin changing state in response to the logic and the user clock. The relative timing of these events can be changed. In addi- tion, the GTS, GSR, and GWE events can be made depen- ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Design Considerations This section contains more detailed design information on the following features. • Delay-Locked Loop . . . see page 20 • BlockRAM . . . see page 24 • ...
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R BUFGDLL Pin Descriptions Use the BUFGDLL macro as the simplest way to provide zero propagation delay for a high-fanout on-chip clock from an external input. This macro uses the IBUFG, CLKDLL and BUFG primitives to implement the most basic ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays 1x Clock Outputs — CLK[0|90|180|270] The 1x clock output pin CLK0 represents a delay-compen- sated version of the source clock (CLKIN) signal. The CLKDLL primitive provides three phase-shifted versions of the ...
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R DLL-3S DLL-3P DLL-2P DLL- DLL-1S DLL-1P DLL-0P DLL-0S Figure 26: Virtex Series DLLs Design Factors Use the following design considerations to avoid pitfalls and improve success ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Virtex-E Device CLKDLL IBUFG CLKIN CLK0 CLK90 CLKFB CLK180 CLK270 IBUFG CLK2X CLKDV RST LOCKED CLKDLL CLKIN CLK0 CLK90 CLKFB CLK180 CLK270 CLK2X CLKDV RST LOCKED Non-Virtex-E Chip Non-Virtex-E Chip Other ...
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R Operating Modes Virtex-E block SelectRAM+ memory supports two operating modes. • Read Through • Write Back Read Through (one clock edge) The read address is registered on the read port clock edge and data appears on the output after ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Port Signals Each block SelectRAM+ port operates independently of the others while accessing the same set of 4096 memory cells. Table 15 describes the depth and width aspect ratios for the ...
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R Conflict Resolution The block SelectRAM+ memory is a true dual-read/write port RAM that allows simultaneous access of the same memory cell from both ports. When one port writes to a given memory cell, the other port must not address ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays CLK ADDR DIN DOUT EN RST WE DISABLED Figure 33: Timing Diagram for Single Port Block SelectRAM+ Memory CLK_A ADDR_A EN_A WE_A DI_A DO_A CLK_B ADDR_B 00 EN_B WE_B DI_B 1111 ...
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R Initialization The block SelectRAM+ memory can initialize during the device configuration sequence. The 16 initialization properties of 64 hex values each (a total of 4096 bits) set the initialization of each RAM. These properties appear in ization properties not ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays VHDL Initialization Example library IEEE; use IEEE.std_logic_1164.all; entity MYMEM is port (CLK, WE:in std_logic; ADDR: in std_logic_vector(8 downto 0); DIN: in std_logic_vector(7 downto 0); DOUT: out std_logic_vector(7 downto 0)); end MYMEM; ...
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R Verilog Initialization Example module MYMEM (CLK, WE, ADDR, DIN, DOUT); input CLK, WE; input [8:0] ADDR; input [7:0] DIN; output [7:0] DOUT; wire logic0, logic1; //synopsys dc_script_begin //set_attribute ram0 INIT_00 "0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string //set_attribute ram0 INIT_01 "FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Fundamentals Modern bus applications, pioneered by the largest and most influential companies in the digital electronics industry, are commonly introduced with a new I/O standard tailored spe- cifically to the needs ...
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R standard requires a Differential Amplifier input buffer and a Push-Pull output buffer. SSTL3 — Stub Series Terminated Logic for 3.3V The Stub Series Terminated Logic for 3 SSTL3 stan- dard is a general purpose 3.3 V memory ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays The voltage reference signal is “banked” within the Virtex-E device on a half-edge basis such that for all packages there are eight independent V banks internally. See REF for a representation ...
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added convenience, the BUFGP can be used to instantiate a high fanout clock input. The BUFGP symbol represents a combination of the LVTTL IBUFG and BUFG symbols, such that the output of the BUFGP can connect directly ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays The LVTTL OBUFT additionally can support one of two slew rate modes to minimize bus transients. By default, the slew rate for each output buffer is reduced to minimize power bus ...
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R IOBUF x133_06_111699 Figure 42: Input/Output Buffer Symbol (IOBUF) The following list details variations of the IOBUF symbol. • IOBUF • IOBUF_S_2 • IOBUF_S_4 • IOBUF_S_6 • IOBUF_S_8 • IOBUF_S_12 • IOBUF_S_16 • IOBUF_S_24 • IOBUF_F_2 ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays IOB Flip-Flop/Latch Property The Virtex-E series I/O block (IOB) includes an optional reg- ister on the input path, an optional register on the output path, and an optional register on the ...
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... CTT AGP Note: This analysis assumes load for each output. Table 22: Pkg/Part BG560 FG676 FG900 www.xilinx.com 1-800-255-7778 Guidelines for Maximum Number of Simultaneously Switching Outputs per Power/Ground Pair Package Standard BGA, FGA Virtex-E Extended Memory Family Equivalent Power/Ground Pairs XCV405E XCV812E 56 Module ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Application Examples Creating a design with the SelectI/O features requires the instantiation of the desired library symbol within the design code. At the board level, designers need to know the termi- ...
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R HSTL A sample circuit illustrating a valid termination technique for HSTL_I appears in Figure 46. A sample circuit illustrating a valid termination technique for HSTL_III appears in Figure 47. HSTL Class 1.5V TT CCO 50Ω ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays SSTL3_I A sample circuit illustrating a valid termination technique for SSTL3_I appears in Figure 49. DC voltage specifications appear in Table 28. SSTL3 Class 3.3V CCO ...
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R SSTL2_II A sample circuit illustrating a valid termination technique for SSTL2_II appears in Figure 52. DC voltage specifications appear in Table 31. SSTL2 Class 1.25V 2.5V CCO 50Ω 25Ω ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays LVTTL LVTTL requires no termination. DC voltage specifications appears in Table 34. Table 34: LVTTL Voltage Specifications Parameter Min V 3.0 CCO V - REF 2.0 IH ...
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R LVDS Depending on whether the device is transmitting an LVDS signal or receiving an LVDS signal, there are two different circuits used for LVDS termination. A sample circuit illustrat- ing a valid termination technique for transmitting LVDS sig- nals ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Termination Resistor Packs Resistor packs are available with the values and the config- uration required for LVDS and LVPECL termination from Bourns, Inc., as listed in Table. For pricing and availability, ...
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R GCLKPAD3 can also be replaced with the package pin name, such as D17 for the BG432 package. Creating LVDS Input Buffers An LVDS input buffer can be placed in a wide number of IOB locations. The exact location is ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Creating LVDS Output Buffers LVDS output buffer can be placed in wide number of IOB locations. The exact location are dependent on the package that is used. The Virtex-E package information ...
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R Creating LVDS Output 3-State Buffers LVDS output 3-state buffers can be placed in a wide number of IOB locations. The exact locations are dependent on the package used. The Virtex-E package information lists the possible locations as IO_L#P for ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays VHDL Instantiation data0_p: IOBUF_LVDS port map (I=>data_out(0), T=>data_tri, IO=>data_p(0), O=>data_int(0)); data0_inv: INV port map (I=>data_out(0), O=>data_n_out(0)); data0_n : IOBUF_LVDS port map (I=>data_n_out(0), T=>data_tri, IO=>data_n(0), O=>open); Verilog Instantiation IOBUF_LVDS data0_p(.I(data_out[0]), .T(data_tri), .IO(data_p[0]), ...
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R Table 44: Bidirectional I/O Library Macros (Continued) Name IOBUFDS_LD_LVDS IOBUFDS_LDE_LVDS IOBUFDS_LDC_LVDS IOBUFDS_LDCE_LVDS IOBUFDS_LDP_LVDS IOBUFDS_LDPE_LVDS Revision History The following table shows the revision history for this document. Date Version 03/23/00 1.0 Initial Xilinx release. 08/01/00 1.1 Accumulated edits and fixes. ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Virtex-E Extended Memory Data Sheet The Virtex-E Extended Memory Data Sheet contains the following modules: • DS025-1, Virtex-E 1.8V Extended Memory FPGAs: Introduction and Ordering Information (Module 1) • DS025-2, Virtex-E ...
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... Contact the factory for design considerations requiring more detailed information. Table 1 Extended Memory device with a corresponding speed file designation. Table 1: Virtex-E Extended Memory Device Device XCV405E XCV812E All specifications are subject to change without notice. (1) Description (2) Plastic packages www.xilinx.com 1-800-255-7778 correlates the current status of each Virtex-E ...
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... V to nominal voltage in 50 ms. For more details on power supply requirements, see XAPP158 . www.xilinx.com Product (Commercial Grade) XCV50E - XCV600E XCV812E - XCV2000E XCV2600E - XCV3200E Virtex-E Family, Industrial Grade Notes: 1. Ramp rate used for this specification is from 0 - 1.8 V DC. Peak current occurs on or near the internal power-on reset threshold and lasts for less than 3 ms ...
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R DC Input and Output Levels Values for V and V are recommended input voltages. Values for operating conditions at the V and V OL all standards meet their specifications. The selected standards are tested at minimum ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays LVDS DC Specifications DC Parameter Supply Voltage Output High Voltage for Q and Q Output Low Voltage for Q and Q Differential Output Voltage (Q – Q High (Q ...
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... T All 0.75 IOPLI XCV405E 1.55 T IOPLID XCV812E 1.55 T All 0. 0. 0.18 IOCKIQ T / All 0. IOPICK T IOICKP XCV405E 1. IOPICKD T XCV812E 1. IOICKPD T / All 0.28 / IOICECK T 0.0 IOCKICE T All 0.38 IOSRCKI T All 0.54 IOSRIQ T All 3.88 GSRQ Table 3. www.xilinx.com 1-800-255-7778 6. (2) Speed Grade - 0.8 ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays IOB Input Switching Characteristics Standard Adjustments Description Data Input Delay Adjustments Standard-specific data input delay adjustments Notes: 1. Input timing i for LVTTL is measured at 1.4 V. For other I/O ...
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R IOB Output Switching Characteristics, Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays with the values shown in (1) Description Propagation Delays O input ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays IOB Output Switching Characteristics Standard Adjustments Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays by ...
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R Calculation Function of Capacitance ioop T is the propagation delay from the O Input of the IOB to the ioop pad. The values for T are based on the standard capacitive ioop load (Csl) for ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Clock Distribution Switching Characteristics Description GCLK IOB and Buffer Global Clock PAD to output. Global Clock Buffer I input to O output I/O Standard Global Clock Input Adjustments (1) Description Data ...
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R CLB Switching Characteristics Delays originating at F/G inputs vary slightly according to the input used, see worst-case. Precise values are provided by the timing analyzer. (1) Description Combinatorial Delays 4-input function: F/G inputs to X/Y outputs 5-input function: F/G ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays F5IN CLK CE Module COUT LUT ...
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R CLB Arithmetic Switching Characteristics Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment listed. Precise values are provided by the timing analyzer. (1) Description Combinatorial Delays F operand inputs to ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays CLB Distributed RAM Switching Characteristics (1) Description Sequential Delays Clock CLK to X/Y outputs (WE active mode Clock CLK to X/Y outputs (WE active mode ...
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R Block RAM Switching Characteristics (1) Description Sequential Delays Clock CLK to DOUT output Setup and Hold Times before Clock CLK ADDR inputs DIN inputs EN input RST input WEN input Clock CLK Minimum Pulse Width, High Minimum Pulse Width, ...
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... Output threshold with 35 pF external capacitive load. For other I/O standards and different loads, see CC Symbol Device T XCV405E ICKOF XCV812E ‘‘IOB Output threshold with 35 pF external capacitive load. For other I/O standards and different loads, see CC www.xilinx.com 1-800-255-7778 (2) Speed Grade ...
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... Symbol Device XCV405E 1.5 / –0.4 PSDLL PHDLL XCV812E 1.5 / –0.4 (3) Symbol Device T /T XCV405E PSFD PHFD XCV812E www.xilinx.com 1-800-255-7778 (2) Speed Grade Min -8 -7 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4 (2) Speed Grade Min - ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays DLL Timing Parameters All devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark timing patterns. The following ...
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R DLL Clock Tolerance, Jitter, and Phase Information All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock mirror configuration and matched drivers. Description Input Clock Period Tolerance Input Clock Jitter Tolerance ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Date Version • Updated speed grade -8 numbers in Virtex-E Electrical Characteristics tables 11/20/00 1.3 (Module 3). • Updated minimums in Table 11 (Module 2), and added notes to Table 12 ...
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R DS025-4 (v1.6) July 17, 2002 Virtex-E Pin Definitions Pin Name Dedicated Pin GCK0, GCK1, Yes GCK2, GCK3 M0, M1, M2 Yes CCLK Yes PROGRAM Yes DONE Yes INIT No BUSY/DOUT No D0/DIN, No D1, D2, D3, D4, D5, D6, ...
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... Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays BG560 Ball Grid Array Packages XCV405E and the XCV812E Virtex-E Extended Memory devices are available in the BG560 BGA package. Pins labeled I0_VREF can be used as either in all parts unless device-dependent as indicated in the footnotes. If the pin is not used can be used as general I/O ...
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... IO_L41N_YY 1 IO_VREF_L41P_YY 1 IO_L42N_YY 1 IO_L42P_YY 1 IO_L43N_Y 1 IO_L43P_Y 1 IO_WRITE_L44N_YY 1 IO_CS_L44P_YY DS025-4 (v1.6) July 17, 2002 Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 1: BG560 BGA — XCV405E and XCV812E Pin# Bank Pin Description C14 2 D14 2 A13 2 E14 2 C13 2 IO_DOUT_BUSY_L45P_YY 1 D13 2 IO_DIN_D0_L45N_YY C12 ...
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... IO_L68P_YY 2 IO_L68N_YY IO_L69P_Y 3 IO_L69N_Y 3 IO_L70P_Y 3 IO_VREF_L70N_Y 3 IO_L71P_Y 3 IO_L71N_Y 3 IO_L72P 3 IO_L72N 3 IO_D4_L73P_YY 3 IO_VREF_L73N_YY 3 IO_L74P_Y 3 IO_L74N_Y 3 IO_L75P 3 IO_L75N 3 IO_L76P_Y 3 IO_VREF_L76N_Y Module Table 1: BG560 BGA — XCV405E and XCV812E Pin# Bank Pin Description IO_D5_L79N_YY R5 3 IO_D6_L80P_YY R4 3 IO_VREF_L80N_YY IO_VREF_L82N_YY AE3 3 IO_VREF_L85N_YY AF3 3 AH3 3 AK3 ...
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... IO_VREF_L107P_YY 4 IO_L107N_YY 4 IO_L108P_Y 4 IO_L108N_Y 4 IO_L109P_YY 4 IO_L109N_YY 4 IO_VREF_L110P_YY 4 IO_L110N_YY DS025-4 (v1.6) July 17, 2002 Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 1: BG560 BGA — XCV405E and XCV812E Pin# Bank Pin Description AJ6 4 AK5 4 AN3 4 AL5 4 AJ7 4 IO_VREF_L113P_YY AM4 4 AM5 4 AK7 ...
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... IO_L136P_Y 5 IO_L136N_Y IO_L137N_YY 6 IO_L137P_YY 6 IO_L138N_Y 6 IO_L138P_Y 6 IO_L139N_Y 6 IO_L139P_Y 6 IO_VREF_L140N_Y 6 IO_L140P_Y 6 IO_L141N_Y Module Table 1: BG560 BGA — XCV405E and XCV812E Pin# Bank Pin Description AK23 6 AL24 6 AN26 6 AJ23 6 IO_VREF_L143N_YY AK24 6 1 AM26 6 AM27 6 AJ24 6 AL26 6 AK25 6 IO_VREF_L146N_Y AN29 6 AJ25 6 AK26 6 AM29 6 IO_VREF_L148N_YY ...
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... IO_L171N_YY 7 IO_L171P_YY 7 IO_L172N_YY 7 IO_VREF_L172P_YY 7 IO_L173N_Y 7 IO_L173P_Y 7 IO_L174N_Y 7 IO_VREF_L174P_Y 7 IO_L175N_Y DS025-4 (v1.6) July 17, 2002 Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 1: BG560 BGA — XCV405E and XCV812E Pin# Bank Pin Description 7 E30 7 F29 7 F33 7 G30 7 IO_VREF_L177P_YY K30 7 U31 7 U32 7 ...
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... VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT 0 VCCO 0 VCCO 0 VCCO Module Table 1: BG560 BGA — XCV405E and XCV812E Pin# Bank Pin Description B18 0 B28 0 C22 1 C24 E12 H30 K32 N29 3 N33 U30 Y31 ...
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... B15 NA B23 NA B27 NA B31 F32 G33 NA J32 NA K1 Notes I/O option only in the XCV812E. REF L2 M33 P1 P33 R32 T1 V33 W2 Y1 Y33 AB1 AC32 www.xilinx.com 1-800-255-7778 Pin# GND AD33 GND AE2 GND AG1 GND AG32 GND AH2 GND AJ33 GND AL32 GND ...
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... VREF_0 √ VREF_0 45 √ √ √ VREF_0 www.xilinx.com 1-800-255-7778 BG560 Package Differential Pin Pair Summary XCV405E and XCV812E √ 0 E20 B21 √ 0 C20 D20 VREF_0 0 E19 B20 NA 0 C19 D19 1 0 D18 A19 1 VREF_0 1 E17 C18 NA GCLK LVDS 3/2 1 B17 C17 ...
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... VREF_3 110 - 111 2 - 112 √ D5 113 √ VREF_3 114 1 - 115 VREF_3 116 - 117 www.xilinx.com 1-800-255-7778 BG560 Package Differential Pin Pair Summary XCV405E and XCV812E 3 AG2 AE4 NA √ 3 AH1 AE5 VREF_3 3 AF4 AJ1 NA 3 AJ2 AF5 2 3 AG4 AK2 1 VREF_3 3 AJ3 ...
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... VREF_6 177 2 - 178 - 179 VREF_6 180 - 181 √ VREF_6 182 √ - Notes the XCV812E the XCV405E - www.xilinx.com 1-800-255-7778 BG560 Package Differential Pin Pair Summary XCV405E and XCV812E 6 AA31 AA30 1 VREF_6 6 Y29 AA32 1 6 Y30 AA33 NA √ 6 W29 ...
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R FG676 Fine-Pitch Ball Grid Array Package XCV405E Virtex-E Extended Memory devices are available in the FG676 fine-pitch BGA package. Pins labeled I0_VREF can be used as either. If the pin is not used can be ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 3: FG676 Fine-Pitch BGA — XCV405E Bank Pin Description 1 IO_L25P_YY 1 IO_L26N_YY 1 IO_VREF_L26P_YY 1 IO_L27N_YY 1 IO_L27P_YY 1 IO_L28N 1 IO_L28P 1 IO_L29N_YY 1 IO_L29P_YY 1 IO_L30N_YY 1 ...
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R Table 3: FG676 Fine-Pitch BGA — XCV405E Bank Pin Description 2 IO_L58P_YY 2 IO_L58N_YY 2 IO_L59P_Y 2 IO_L59N_Y 2 IO_L60P_Y 2 IO_L60N_Y 2 IO_L61P_Y 2 IO_L61N_Y 2 IO_L62P_Y 2 IO_L62N_Y 2 IO_VREF_L63P_YY 2 IO_D3_L63N_YY 2 IO_L64P_YY 2 IO_L64N_YY 2 ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 3: FG676 Fine-Pitch BGA — XCV405E Bank Pin Description 3 IO_L90P_YY 3 IO_L90N_YY 3 IO_D7_L91P_YY 3 IO_INIT_L91N_YY 4 GCK0 IO_L92P_YY 4 ...
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R Table 3: FG676 Fine-Pitch BGA — XCV405E Bank Pin Description 5 IO_L118N_YY 5 IO_L119P_YY 5 IO_VREF_L119N_YY 5 IO_L120P_YY 5 IO_L120N_YY 5 IO_L121P 5 IO_L121N 5 IO_L122P_YY 5 IO_L122N_YY 5 IO_L123P_YY 5 IO_L123N_YY 5 IO_L124P_Y 5 IO_L124N_Y 5 IO_L125P_YY 5 ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 3: FG676 Fine-Pitch BGA — XCV405E Bank Pin Description 6 IO_L150P_YY 6 IO_L151N_Y 6 IO_L151P_Y 6 IO_L152N_Y 6 IO_L152P_Y 6 IO_L153N_Y 6 IO_L153P_Y 6 IO_L154N_Y 6 IO_L154P_Y 6 IO_VREF_L155N_YY 6 ...
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R Table 3: FG676 Fine-Pitch BGA — XCV405E Bank Pin Description 7 IO_L182P_YY 2 CCLK 3 DONE NA DXN NA DXP PROGRAM NA TCK NA TDI 2 TDO NA TMS ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 3: FG676 Fine-Pitch BGA — XCV405E Bank Pin Description ...
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R Table 3: FG676 Fine-Pitch BGA — XCV405E Bank Pin Description 1 VCCO 2 VCCO 2 VCCO 2 VCCO 2 VCCO 2 VCCO 2 VCCO 3 VCCO 3 VCCO 3 VCCO 3 VCCO 3 VCCO 3 VCCO 4 VCCO 4 ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 3: FG676 Fine-Pitch BGA — XCV405E Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA ...
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R FG676 Differential Pin Pairs Virtex-E Extended Memory devices have differential pin pairs that can also provide other functions when not used as a differential pair. A √ in the AO column indicates that the pin pair can be used ...
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 4: FG676 Fine-Pitch BGA Differential Pin Pair Summary — XCV405E P N Pair Bank Pin Pin 50 2 F23 G23 51 2 H23 J20 52 2 G24 H22 53 2 ...
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R Table 4: FG676 Fine-Pitch BGA Differential Pin Pair Summary — XCV405E P N Pair Bank Pin Pin 118 5 AA12 AD12 119 5 AC12 AB12 120 5 AD11 Y12 121 5 AB11 AD10 122 5 AC11 AE10 123 5 ...
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... Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays FG900 Fine-Pitch Ball Grid Array Package The XCV812E Virtex-E Extended Memory devices are available in the FG900 fine-pitch BGA package. Pins labeled I0_VREF can be used as either. If the pin is not used can be used as general I/O. Immediately ...
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... IO_L39N 1 IO_L39P 1 IO_L40N 1 IO_L40P 1 IO_L41N_YY 1 IO_VREF_L41P_YY 1 IO_L42N_YY 1 IO_L42P_YY 1 IO_L43N DS025-4 (v1.6) July 17, 2002 Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 5: FG900 Fine-Pitch BGA Package — XCV812E Pin Bank D14 1 B14 1 A14 1 J14 1 K14 1 IO_VREF_L45P_YY J15 1 A15 1 1 E15 ...
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... IO_DOUT_BUSY_L70P_YY 2 IO_DIN_D0_L70N_YY 2 IO_L72P_Y 2 IO_L72N_Y 2 IO_L73P 2 IO_L73N 2 IO_L75P 2 IO_L75N 2 IO_VREF_L76P_Y Module Table 5: FG900 Fine-Pitch BGA Package — XCV812E Pin Bank A26 2 B26 2 K20 2 D25 2 J21 2 B27 2 G23 2 A27 2 IO_VREF_L80P_YY F24 2 K21 2 C27 2 2 D28 2 F27 2 H25 2 J25 2 IO_VREF_L84P J28 2 K28 2 K30 2 M23 ...
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... IO_L107N 3 IO_L108P 3 IO_L108N 3 IO_L109P 3 IO_VREF_L109N 3 IO_L110P 3 IO_L110N 3 IO_L111P_Y 3 IO_L111N_Y DS025-4 (v1.6) July 17, 2002 Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 5: FG900 Fine-Pitch BGA Package — XCV812E Pin Bank N25 3 N27 3 N30 3 IO_D4_L113P_YY P21 3 IO_VREF_L113N_YY N26 3 P28 3 P29 3 N24 ...
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... IO_L138P 3 IO_L138N 3 IO_L139P_Y 3 IO_L139N_Y 3 IO_D7_L141P_YY 3 IO_INIT_L141N_YY 4 GCK0 IO_VREF_4 4 IO_L142P_YY Module Table 5: FG900 Fine-Pitch BGA Package — XCV812E Pin Bank Y22 4 AC27 4 AD28 4 AB25 4 AC26 4 AE30 4 AD27 4 AF30 4 IO_VREF_4_L148P_YY AF29 4 AB24 4 AB23 4 AE28 4 AE26 4 AG29 4 AH30 4 AC24 4 IO_VREF_4_L152P_YY AH29 4 AA22 4 4 AJ16 4 ...
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... IO_L176N 4 IO_LVDS_DLL_L177P 5 GCK1 IO_LVDS_DLL_L177N 5 IO_L179P DS025-4 (v1.6) July 17, 2002 Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 5: FG900 Fine-Pitch BGA Package — XCV812E Pin Bank AE19 5 AK22 5 AH20 5 IO_VREF_5_L180N_YY AG19 5 AB17 5 AJ19 5 AD17 5 AA16 5 AA17 5 AK21 5 AB16 5 IO_VREF_5_L184N_YY AG18 ...
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... IO_L205P 5 IO_L205N 5 IO_L206P_YY 5 IO_VREF_5_L206N_YY 5 IO_L207P_YY 5 IO_L207N_YY 5 IO_L209P_Y 5 IO_L209N_Y 5 IO_L210P_Y 5 IO_L210N_Y Module Table 5: FG900 Fine-Pitch BGA Package — XCV812E Pin Bank AF9 6 AH9 6 AK9 6 AF8 6 AB11 6 AC11 6 AG8 6 AK8 6 AF7 6 AG7 6 AK7 6 IO_VREF_L218N_Y AJ7 6 AD10 6 AH6 6 AC10 6 AD9 6 AG6 6 AB10 6 AJ5 6 IO_VREF_L222N_YY ...
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... IO_L238P 6 IO_L239N 6 IO_L239P 6 IO_VREF_L240N_YY 6 IO_L240P_YY 6 IO_L241N_YY 6 IO_L241P_YY 6 IO_L242N_Y 6 IO_L242P_Y 6 IO_L243N 6 IO_L243P 6 IO_VREF_L244N 6 IO_L244P 6 IO_L246N 6 IO_L246P 6 IO_L247N DS025-4 (v1.6) July 17, 2002 Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 5: FG900 Fine-Pitch BGA Package — XCV812E Pin Bank AA6 AB2 IO_VREF_L255P_YY ...
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... IO_L268N 7 IO_L268P 7 IO_L269N 7 IO_VREF_L269P 7 IO_L270N 7 IO_L270P 7 IO_L271N_Y 7 IO_L271P_Y 7 IO_L272N_YY 7 IO_L272P_YY 7 IO_L273N_YY 7 IO_VREF_L273P_YY 7 IO_L274N 7 IO_L274P 7 IO_L275N 7 IO_L275P 7 IO_L276N_YY 7 IO_L276P_YY 7 IO_L277N_Y 7 IO_VREF_L277P_Y 7 IO_L278N 7 IO_L278P 7 IO_L280N 7 IO_L280P 7 IO_L281N_Y 7 IO_L281P_Y 2 DONE NA DXN NA DXP 3 CCLK Module Table 5: FG900 Fine-Pitch BGA Package — XCV812E Pin Bank AJ28 ...
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... NA VCCO_1 NA VCCO_1 NA VCCO_1 NA VCCO_2 NA VCCO_2 NA VCCO_2 NA VCCO_2 NA VCCO_2 NA VCCO_2 DS025-4 (v1.6) July 17, 2002 Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 5: FG900 Fine-Pitch BGA Package — XCV812E Pin Bank V16 NA V17 NA V18 NA W11 NA W12 NA W19 NA W20 NA Y11 NA Y12 NA Y19 ...
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... GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND Module Table 5: FG900 Fine-Pitch BGA Package — XCV812E Pin Bank F2 NA R12 NA P12 NA N12 NA R11 NA P11 Y18 NA AH7 NA AK30 NA AJ30 NA B30 NA A30 NA AK29 NA AJ29 NA ...
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... R Table 5: FG900 Fine-Pitch BGA Package — XCV812E Bank Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND DS025-4 (v1.6) July 17, 2002 Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays ...
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... A24 - √ B24 C24 √ G22 H21 61 1 C25 E23 - 62 1 A26 D24 - √ K20 B26 √ J21 D25 √ G23 B27 Module Table 6: FG900 Differential Pin Pair Summary — XCV812E Other Functions Pair Bank - VREF VREF 76 2 GCLK LVDS 3 VREF ...
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... AE23 AB20 - 154 4 AC20 AG23 - √ 155 4 AF22 AE22 DS025-4 (v1.6) July 17, 2002 Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 6: FG900 Differential Pin Pair Summary — XCV812E Other Functions Pair Bank VREF 156 4 - 158 4 - 160 4 - 162 4 VREF 163 ...
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... 239 √ 240 6 T8 AB2 √ 241 √ 242 243 244 246 Module Table 6: FG900 Differential Pin Pair Summary — XCV812E Other Functions Pair Bank - 247 7 VREF 249 7 - 250 7 - 251 7 - 252 7 VREF 253 7 - 254 7 - 255 7 - 256 7 - 257 7 - 258 7 - 259 7 - 260 7 ...
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... Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays XCV405E 404 404 Figure 1 Temperature Range C = Commercial ( Industrial (T Number of Pins Package Type BG = Ball Grid Array FG = Fine Pitch Ball Grid Array Figure 1: Virtex Ordering Information www.xilinx.com 1-800-255-7778 XCV812E 404 556 = 0˚C to +85˚ −40˚C to +100˚C) J DS025_001_112000 Module ...
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... Virtex-E Switching Characteristics section. • DS025-3, Virtex-E 1.8V Extended Memory FPGAs: DC and Switching Characteristics (Module 3) • DS025-4, Virtex-E 1.8V Extended Memory FPGAs: Pinout Tables (Module 4) www.xilinx.com 1-800-255-7778 tables. Virtex-E Extended Memory Data Table 1 for XCV405E and the XCV812E devices. DS025-4 (v1.6) July 17, 2002 R ...