XC5VLX110-1FF676I Xilinx Inc, XC5VLX110-1FF676I Datasheet - Page 230

• Manufacturer Part Number: XC5VLX110-1FF676I
• Description: IC FPGA VIRTEX-5 110K 676FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX110-1FF676I

• Number Of Logic Elements/cells: 110592
• Number Of Labs/clbs: 8640
• Total Ram Bits: 4718592
• Number Of I /o: 440
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 676-BBGA, FCBGA
• For Use With: HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF676-500-G - BOARD DEV VIRTEX 5 FF676
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 6: SelectIO Resources
230
DCI Usage Examples
4.
5.
6.
7.
The behavior of a DCI 3-state outputs is as follows:
If a LVDCI or LVDCI_DV2 driver is in 3-state, the driver is 3-stated. If a driver with single
or split termination is in 3-state, the driver is 3-stated but the termination resistor remains.
The following section lists actions that must be taken for each DCI I/O standard.
•
•
•
•
The value of the external reference resistors should be selected to give the desired
output impedance. If using GTL_DCI, HSTL_DCI, or SSTL_DCI I/O standards, then
the external reference resistors should be 50 Ω .
The values of the reference resistors must be within the supported range
(20 Ω – 100 Ω).
Follow the DCI I/O banking rules:
a.
b. V
c.
d. No more than one DCI I/O standard using split termination type is allowed per
e.
Master DCI is not supported in Banks 1 and 2.
Figure 6-16
HSTL_III_DCI, and HSTL_IV_DCI I/O standards.
Figure 6-17
SSTL2_II_DCI I/O standards.
DCI outputs that do not require reference resistors on VRP/VRN:
HSTL_I_DCI
HSTL_III_DCI
HSTL_I_DCI_18
HSTL_III_DCI_18
SSTL2_I_DCI
SSTL18_I_DCI
DCI inputs that do not require reference resistors on VRP/VRN:
LVDCI_15
LVDCI_18
LVDCI_25
LVDCI_33
LVDCI_DV2_15
LVDCI_DV2_18
LVDCI_DV2_25
V
No more than one DCI I/O standard using single termination type is allowed per
bank.
bank.
Single termination and split termination, controlled impedance driver, and
controlled impedance driver with half impedance can co-exist in the same bank.
REF
CCO
must be compatible for all of the inputs in the same bank.
must be compatible for all of the inputs and outputs in the same bank.
provides examples illustrating the use of the HSTL_I_DCI, HSTL_II_DCI,
provides examples illustrating the use of the SSTL2_I_DCI and
www.xilinx.com
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010