XC5VLX110T-1FFG1136C Xilinx Inc, XC5VLX110T-1FFG1136C Datasheet - Page 365
![IC FPGA VIRTEX-5 110K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX110T-1FFG1136C
Manufacturer Part Number
XC5VLX110T-1FFG1136C
Description
IC FPGA VIRTEX-5 110K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110T-1FFG1136C
Total Ram Bits
5455872
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
No. Of Logic Blocks
17280
No. Of Gates
110000
Family Type
Virtex-5 LXT
No. Of Speed Grades
1
No. Of I/o's
640
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX110T-1FFG1136C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Company:
Part Number:
XC5VLX110T-1FFG1136CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- XC5VLX30T-1FFG665C_PRODUCT_CHANGE PDF datasheet #4
- Current page: 365 of 385
- Download datasheet (14Mb)
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ISERDES VHDL and Verilog Instantiation Template
X-Ref Target - Figure 8-9
Clock Event 2
The reset pulse is deasserted on the rising edge of CLKDIV. The difference in propagation
delay between the two ISERDES causes the RST input to come out of reset on two different
CLK cycles. Without internal retiming, ISERDES1 finishes reset one CLK cycle before
ISERDES0 and both ISERDES are asynchronous.
Clock Event 3
The release of the reset signal at the RST input is retimed internally to CLKDIV. This
synchronizes ISERDES0 and ISERDES1.
Clock Event 4
The release of the reset signal at the RST input is retimed internally to CLK.
VHDL and Verilog instantiation templates are available in the Libraries Guide for all
primitives and submodules.
In VHDL, each template has a component declaration section and an architecture section.
Each part of the template should be inserted within the VHDL design file. The port map of
the architecture section should include the design signal names.
Figure 8-9: Two ISERDES Coming Out of Reset Synchronously with One Another
Internal Reset
Internal Reset
RST Input
(CLKDIV)
Signal at
(CLK)
www.xilinx.com
ISERDES0
ISERDES1
ISERDES0
ISERDES1
ISERDES0
ISERDES1
CLKDIV
CLK
Input Serial-to-Parallel Logic Resources (ISERDES)
Event 1
Clock
Event 2
Clock
Event 3
Clock
Clock
Event 4
UG190_8_09_110707
365
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