XC5VLX110T-1FFG1136C Xilinx Inc, XC5VLX110T-1FFG1136C Datasheet - Page 301
![IC FPGA VIRTEX-5 110K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX110T-1FFG1136C
Manufacturer Part Number
XC5VLX110T-1FFG1136C
Description
IC FPGA VIRTEX-5 110K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110T-1FFG1136C
Total Ram Bits
5455872
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
No. Of Logic Blocks
17280
No. Of Gates
110000
Family Type
Virtex-5 LXT
No. Of Speed Grades
1
No. Of I/o's
640
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX110T-1FFG1136C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Company:
Part Number:
XC5VLX110T-1FFG1136CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- XC5VLX30T-1FFG665C_PRODUCT_CHANGE PDF datasheet #4
- Current page: 301 of 385
- Download datasheet (14Mb)
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Table 6-39: I/O Compatibility (Continued)
Notes:
1. See
2. Differential inputs and inputs using V
3. N/R = no requirement.
4. RSDS_25 has the same DC specifications as LVDS_25. All information pertaining to LVDS_25
5. I/O standard is selected using the IOSTANDARD attribute.
HSTL_III
HSTL_IV
HSTL_I
HSTL_II
DIFF_HSTL_I
DIFF_HSTL_II
LVCMOS15
LVDCI_15
HSLVDCI_15
LVDCI_DV2_15
GTLP_DCI
HSTL_III_DCI
HSTL_IV_DCI
HSTL_I_DCI
HSTL_II_DCI
HSTL_II_T_DCI
DIFF_HSTL_I_DCI
DIFF_HSTL_II_DCI
GTL_DCI
GTLP
GTL
LVCMOS12
HSTL_I_12
must not exceed V
is applicable to RSDS_25.
I/O Standard
3.3V I/O Design Guidelines
CCO
, due to the presence of clamp diodes to V
www.xilinx.com
Output
N/R
1.5
1.2
1.2
for more detailed information
V
Rules for Combining I/O Standards in the Same Bank
CCO
REF
Note (2)
Note (2)
Input
are powered from V
1.5
1.2
1.2
V
Input
V
N/R
N/R
N/R
N/R
CCO
N/R
N/R
N/R
N/R
0.75
0.75
0.75
0.75
0.75
0.9
0.9
0.9
0.9
0.8
0.8
0.6
REF
1
1
/2
CCAUX
CCO
Output
Single
Single
Single
Series
Series
Series
Termination Type
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
Split
Split
.
. However, pin voltage
Single
Single
Single
Single
Input
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
Split
Split
Split
Split
Split
N/R
N/R
N/R
N/R
301
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