XC5VLX110T-1FFG1136C Xilinx Inc, XC5VLX110T-1FFG1136C Datasheet - Page 292

• Manufacturer Part Number: XC5VLX110T-1FFG1136C
• Description: IC FPGA VIRTEX-5 110K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX110T-1FFG1136C

• Total Ram Bits: 5455872
• Number Of Logic Elements/cells: 110592
• Number Of Labs/clbs: 8640
• Number Of I /o: 640
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 17280
• No. Of Gates: 110000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 640
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Chapter 6: SelectIO Resources
X-Ref Target - Figure 6-84
X-Ref Target - Figure 6-85
292
DIFF_SSTL18_II_DCI
DIFF_SSTL18_II_DCI
DIFF_SSTL18_II_DCI
DCI
External Termination
DIFF_SSTL18_II
DIFF_SSTL18_II
DIFF_SSTL18_II
R 0 = 20
R 0 = 20
Figure 6-85: Differential SSTL (1.8V) Class II with DCI Bidirectional Termination
Ω
Ω
+
–
Figure 6-84: Differential SSTL (1.8V) Class II with Bidirectional Termination
+
–
2R
2R
2R
2R
Figure 6-84
differential SSTL Class II (1.8V) with bidirectional termination.
Figure 6-85
differential SSTL Class II (1.8V) with bidirectional DCI termination.
VRN
VRP
VRN
VRP
IOB
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
V
V
shows a sample circuit illustrating a valid termination technique for
shows a sample circuit illustrating a valid termination technique for
CCO
CCO
20Ω
20Ω
= 1.8V
= 1.8V
V
V
TT
TT
IOB
= 0.9V
= 0.9V
www.xilinx.com
50Ω
50Ω
Z 0
Z 0
Z 0
Z 0
V
TT
50Ω
V
50Ω
TT
IOB
= 0.9V
V
CCO
= 0.9V
V
CCO
= 1.8V
2R
2R
2R
2R
= 1.8V
VRP
VRN
VRP
VRN
20Ω
20Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
IOB
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
DIFF_SSTL18_II_DCI
DIFF_SSTL18_II_DCI
DIFF_SSTL18_II_DCI
DIFF_SSTL18_II
DIFF_SSTL18_II
DIFF_SSTL18_II
+
–
R 0 = 20
+
–
ug190_6_79_091807
R 0 = 20
ug190_6_80_030506
Ω
Ω