XCV405E-7BG560I Xilinx Inc, XCV405E-7BG560I Datasheet - Page 72

• Manufacturer Part Number: XCV405E-7BG560I
• Description: IC FPGA 1.8V 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV405E-7BG560I

• Number Of Logic Elements/cells: 10800
• Number Of Labs/clbs: 2400
• Total Ram Bits: 573440
• Number Of I /o: 404
• Number Of Gates: 129600
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Virtex-E Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLL
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DLL
Module 3 of 4
16
Notes:
1.
2.
3.
Notes:
1.
2.
LVTTL Global Clock Input to Output Delay using
Output Flip-flop, 12 mA, Fast Slew Rate, with
DLL.
For data output with different standards, adjust
the delays with the values shown in
Switching Characteristics Standard Adjustments’’
on page
LVTTL Global Clock Input to Output Delay using
Output Flip-flop, 12 mA, Fast Slew Rate, without
DLL.
For data output with different standards, adjust
the delays with the values shown in
Switching Characteristics Standard Adjustments’’
on page
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at 50% V
Table 2
DLL output jitter is already included in the timing calculation.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at 50% V
Table 2
8.
8.
and
and
Table
Table
Description
Description
3.
3.
(1)
(1)
CC
CC
‘‘IOB Output
‘‘IOB Output
threshold with 35 pF external capacitive load. For other I/O standards and different loads, see
threshold with 35 pF external capacitive load. For other I/O standards and different loads, see
T
Symbol
Symbol
www.xilinx.com
ICKOFDLL
1-800-255-7778
T
ICKOF
XCV405E
XCV812E
XCV405E
XCV812E
Device
Device
(3)
Min
Min
1.0
1.0
1.6
1.8
Speed Grade
Speed Grade
3.1
3.1
4.5
4.8
-8
-8
DS025-3 (v2.3.2) March 14, 2003
3.1
3.1
4.7
5.0
-7
-7
(2)
(2)
3.1
3.1
4.9
5.2
-6
-6
Units
Units
ns
ns
ns
ns
R