XCV405E-7BG560I Xilinx Inc, XCV405E-7BG560I Datasheet - Page 51

• Manufacturer Part Number: XCV405E-7BG560I
• Description: IC FPGA 1.8V 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV405E-7BG560I

• Number Of Logic Elements/cells: 10800
• Number Of Labs/clbs: 2400
• Total Ram Bits: 573440
• Number Of I /o: 404
• Number Of Gates: 129600
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

GCLKPAD3 can also be replaced with the package pin
name, such as D17 for the BG432 package.
Creating LVDS Input Buffers
An LVDS input buffer can be placed in a wide number of IOB
locations. The exact location is dependent on the package
that is used. The Virtex-E package information lists the pos-
sible locations as IO_L#P for the P-side and IO_L#N for the
N-side where # is the pair number.
HDL Instantiation
Only one input buffer is required to be instantiated in the
design and placed on the correct IO_L#P location. The
N-side of the buffer is reserved and no other IOB is allowed
to be placed on this location. In the physical device, a con-
figuration option is enabled that routes the pad wire from the
IO_L#N IOB to the differential input buffer located in the
IO_L#P IOB. The output of this buffer then drives the output
of the IO_L#P cell or the input register in the IO_L#P IOB. In
EPIC it appears that the second buffer is unused. Any
attempt to use this location for another purpose leads to a
DRC error in the software.
VHDL Instantiation
Verilog Instantiation
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the input buffers this can be done with the following con-
straint in the UCF or NCF file.
Optional N-side
Some designers might prefer to also instantiate the N-side
buffer for the input buffer. This allows the top-level net list to
include net connections for both PCB layout and sys-
tem-level integration. In this case, only the output P-side
IBUF connection has a net connected to it. Since the N-side
IBUF does not have a connection in the EDIF net list, it is
trimmed from the design in MAP.
VHDL Instantiation
Verilog Instantiation
DS025-2 (v2.3) November 19, 2002
data0_p : IBUF_LVDS port map (I=>data(0),
O=>data_int(0));
IBUF_LVDS data0_p (.I(data[0]),
.O(data_int[0]));
NET data<0> LOC = D28; # IO_L0P
data0_p : IBUF_LVDS port map
(I=>data_p(0), O=>data_int(0));
data0_n : IBUF_LVDS port map
(I=>data_n(0), O=>open);
IBUF_LVDS data0_p (.I(data_p[0]),
.O(data_int[0]));
IBUF_LVDS data0_n (.I(data_n[0]), .O());
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
www.xilinx.com
1-800-255-7778
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the global clock input buffers this can be done with the fol-
lowing constraint in the UCF or NCF file.
Adding an Input Register
All LVDS buffers can have an input register in the IOB. The
input register is in the P-side IOB only. All the normal IOB
register options are available (FD, FDE, FDC, FDCE, FDP,
FDPE, FDR, FDRE, FDS, FDSE, LD, LDE, LDC, LDCE,
LDP, LDPE). The register elements can be inferred or
explicitly instantiated in the HDL code.
The register elements can be packed in the IOB using the
IOB property to TRUE on the register or by using “map -pr
[i|o|b]”, where “i” is inputs only, “o” is outputs only, and “b” is
both inputs and outputs.
To improve design coding times VHDL and Verilog synthe-
sis macro libraries available to explicitly create these struc-
tures. The input library macros are listed in
and IB inputs to the macros are the external net connec-
tions.
Table 42:
IBUFDS_FD_LVDS
IBUFDS_FDE_LVDS
IBUFDS_FDC_LVDS
IBUFDS_FDCE_LVDS
IBUFDS_FDP_LVDS
IBUFDS_FDPE_LVDS
IBUFDS_FDR_LVDS
IBUFDS_FDRE_LVDS
IBUFDS_FDS_LVDS
IBUFDS_FDSE_LVDS
IBUFDS_LD_LVDS
IBUFDS_LDE_LVDS
IBUFDS_LDC_LVDS
IBUFDS_LDCE_LVDS
IBUFDS_LDP_LVDS
IBUFDS_LDPE_LVDS
NET data_p<0> LOC = D28; # IO_L0P
NET data_n<0> LOC = B29; # IO_L0N
Name
Input Library Macros
I, IB, CE, C, PRE
I, IB, GE, G, CLR
I, IB, GE, G, PRE
I, IB, CE, C, CLR
I, IB, CE, C, R
I, IB, CE, C, S
I, IB, G, PRE
I, IB, C, CLR
I, IB, C, PRE
I, IB, G, CLR
I, IB, GE, G
I, IB, CE, C
I, IB, C, R
I, IB, C, S
I, IB, G
Inputs
I, IB, C
Table
Module 2 of 4
Outputs
42. The I
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
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Q
Q
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47