XCV405E-7BG560I Xilinx Inc, XCV405E-7BG560I Datasheet - Page 7

• Manufacturer Part Number: XCV405E-7BG560I
• Description: IC FPGA 1.8V 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV405E-7BG560I

• Number Of Logic Elements/cells: 10800
• Number Of Labs/clbs: 2400
• Total Ram Bits: 573440
• Number Of I /o: 404
• Number Of Gates: 129600
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IOBs, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.
Eight I/O banks result from separating each edge of the
FPGA into two banks, as shown in
multiple V
same voltage. This voltage is determined by the output
standards in use.
Within a bank, output standards can be mixed only if they
use the same V
Table
their open-drain outputs do not depend on V
Table 2:
DS025-2 (v2.3) November 19, 2002
V
3.3 V
2.5 V
1.8 V
1.5 V
CCO
2. GTL and GTL+ appear under all voltages because
PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL,
CCO
SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+,
R
Compatible Output Standards
HSTL I, HSTL III, HSTL IV, GTL, GTL+
Figure 3: Virtex-E I/O Banks
pins, all of which must be connected to the
CCO
Bank 0
Bank 5
. Compatible standards are shown in
LVCMOS18, GTL, GTL+
Compatible Standards
GCLK3 GCLK2
GCLK1 GCLK0
VirtexE
Device
GTL+, LVPECL
BLVDS, LVDS
Bank 1
Bank 4
Figure
ds022_03_121799
3. Each bank has
CCO
.
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
www.xilinx.com
1-800-255-7778
Some input standards require a user-supplied threshold
voltage, V
matically configured as inputs for the V
imately one in six of the I/O pins in the bank assume this
role.
The V
and consequently only one V
each bank. All V
nected to the external voltage source for correct operation.
Within a bank, inputs that require V
those that do not. However, only one V
used within a bank.
In
LVCMOS18, PCI33_3, PCI66_3 standards are supplied by
V
and output buffers that have the same V
together.
The V
pin-out tables and diagrams. The diagrams also show the
bank affiliation of each I/O.
Within a given package, the number of V
can vary depending on the size of device. In larger devices,
more I/O pins convert to V
a super set of the V
possible to design a PCB that permits migration to a larger
device if necessary. All the V
anticipated must be connected to the V
used for I/O.
In smaller devices, some V
do not connect within the package. These unconnected pins
can be left unconnected externally, or they can be con-
nected to the V
device, if necessary.
Configurable Logic Block
The basic building block of the Virtex-E CLB is the logic cell
(LC). An LC includes a 4-input function generator, carry
logic, and a storage element. The output from the function
generator in each LC drives both the CLB output and the D
input of the flip-flop. Each Virtex-E CLB contains four LCs,
organized in two similar slices, as shown in
Figure 5
CCO
Virtex-E,
CCO
REF
rather than V
shows a more detailed view of a single slice.
REF
and V
pins within a bank are interconnected internally
. In this case, certain user-I/O pins are auto-
input
CCO
REF
REF
pins in the bank, however, must be con-
CCINT
REF
pins for each bank appear in the device
voltage to permit migration to a larger
buffers
pins used for smaller devices, it is
. For these standards, only input
REF
CCO
REF
REF
pins. Since these are always
with
pins used in larger devices
voltage can be used within
pins for the largest device
REF
LVTTL,
REF
REF
REF
REF
can be mixed with
CCO
voltage. Approx-
voltage, and not
voltage can be
and V
can be mixed
Module 2 of 4
LVCMOS2,
Figure
CCO
pins
4.
3