XC4VFX60-11FFG672C Xilinx Inc, XC4VFX60-11FFG672C Datasheet - Page 58
XC4VFX60-11FFG672C
Manufacturer Part Number
XC4VFX60-11FFG672C
Description
IC FPGA VIRTEX-4 FX 60K 672-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX60-11FFG672C
Number Of Logic Elements/cells
56880
Number Of Labs/clbs
6320
Total Ram Bits
4276224
Number Of I /o
352
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-BBGA, FCBGA
For Use With
HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 2: Digital Clock Managers (DCMs)
58
DCM_BASE Primitive
DCM_PS Primitive
DCM_ADV Primitive
The DCM_BASE primitive accesses the basic frequently used DCM features and simplifies
the user-interface ports. The clock deskew, frequency synthesis, and fixed-phase shifting
features are available to use with DCM_BASE.
DCM_BASE primitive.
Table 2-2: DCM_BASE Primitive
The DCM_PS primitive accesses all DCM features and ports available in DCM_BASE plus
additional ports used by the variable phase shifting feature. DCM_PS also has the
following available DCM features: clock deskew, frequency synthesis, and fixed or
variable phase-shifting.
Table 2-3: DCM_PS Primitive
The DCM_ADV primitive has access to all DCM features and ports available in DCM_PS
plus additional ports for the dynamic reconfiguration feature. It is a superset of the other
two DCM primitives. DCM_ADV uses all the DCM features including clock deskew,
frequency synthesis, fixed or variable phase shifting, and dynamic reconfiguration.
Table 2-4
Table 2-4: DCM_ADV Primitive
Clock Input
Control and Data Input
Clock Output
Status and Data Output
Clock Input
Control and Data Input
Clock Output
Status and Data Output
Clock Input
Control and Data Input
Clock Output
Status and Data Output
Available Ports
Available Ports
Available Ports
lists the available ports in the DCM_ADV primitive.
Table 2-3
www.xilinx.com
CLKIN, CLKFB
RST
CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV,
CLKFX, CLKFX180
LOCKED
CLKIN, CLKFB, PSCLK
RST, PSINCDEC, PSEN
CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV,
CLKFX, CLKFX180
LOCKED, PSDONE, DO[15:0]
CLKIN, CLKFB, PSCLK, DCLK
RST, PSINCDEC, PSEN, DADDR[6:0], DI[15:0], DWE, DEN
CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV,
CLKFX, CLKFX180
LOCKED, PSDONE, DO[15:0], DRDY
lists the available ports in the DCM_PS primitive.
Table 2-2
Port Names
Port Names
Port Names
lists the available ports in the
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
R
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