XC4VFX60-11FFG672C Xilinx Inc, XC4VFX60-11FFG672C Datasheet - Page 195
XC4VFX60-11FFG672C
Manufacturer Part Number
XC4VFX60-11FFG672C
Description
IC FPGA VIRTEX-4 FX 60K 672-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX60-11FFG672C
Number Of Logic Elements/cells
56880
Number Of Labs/clbs
6320
Total Ram Bits
4276224
Number Of I /o
352
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-BBGA, FCBGA
For Use With
HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Shift Register Data Flow
The block diagrams of the shift register (SRL16E) and the cascadable shift register
(SRLC16E) are illustrated in
located in the
Shift Operation
The shift operation is a single clock-edge operation, with an active High clock enable
feature. When enable is High, the input (D) is loaded into the first bit of the shift register,
and each bit is shifted to the next highest bit position. In a cascadable shift register
configuration (such as SRLC16), the last bit is shifted out on the Q15 output.
The bit selected by the 4-bit address appears on the Q output.
Dynamic Read Operation
The Q output is determined by the 4-bit address. Each time a new address is applied to the
4-input address pins, the new bit position value is available on the Q output after the time
delay to access the LUT. This operation is asynchronous and independent of the clock and
clock enable signals.
Static Read Operation
If the 4-bit address is fixed, the Q output always uses the same bit position. This mode
implements any shift-register length from one to 16 bits in one LUT. Shift register length is
(N+1) where N is the input address.
The Q output changes synchronously with each shift operation. The previous bit is shifted
to the next position and appears on the Q output.
Address
Figure 5-12: Simplified Shift Register and Cascadable Shift Register
CLK
CE
D
“SRL Primitives and Submodules”
SRL16E
www.xilinx.com
Figure
5-12. The pin descriptions of SRL16E and SRLC16E are
Q
Address
Address
CLK
CLK
section.
CE
CE
D
D
SRLC16E
SRLC16E
UG070_5_12_071504
CLB Overview
Q15
Q
Q
Q15
195
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