XC4VFX60-11FFG672C Xilinx Inc, XC4VFX60-11FFG672C Datasheet - Page 387
XC4VFX60-11FFG672C
Manufacturer Part Number
XC4VFX60-11FFG672C
Description
IC FPGA VIRTEX-4 FX 60K 672-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX60-11FFG672C
Number Of Logic Elements/cells
56880
Number Of Labs/clbs
6320
Total Ram Bits
4276224
Number Of I /o
352
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-BBGA, FCBGA
For Use With
HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
3-State Parallel-to-Serial Conversion
order data input pin to highest (i.e., data on the D1 input pin is the first bit transmitted at
the OQ pins). The data parallel-to-serial converter is available in two modes; single-data
rate (SDR) and double-data rate (DDR).
The OSERDES uses two clocks, CLK and CLKDIV, for data rate conversion. CLK is the
high-speed serial clock, CLKDIV is the divided parallel clock. It is assumed that CLK and
CLKDIV are phase aligned. It is required that a reset be applied to the OSERDES prior to
use. The OSERDES contains an internal counter that controls dataflow, and failure to
synchronize the reset with the CLKDIV results in unexpected output.
the relationship between CLK and CLKDIV in all modes.
Table 8-6: CLK/CLKDIV Relationship of the Data Parallel-to-Serial Converter
In addition to parallel-to-serial conversion of data, an OSERDES module also contains a
parallel-to-serial converter for 3-state control of the IOB. Unlike data conversion, the
3-state converter can only serialize up to four bits of parallel 3-state signals. The 3-state
converter cannot be cascaded.
Input Data Width Output in SDR
Mode
2
3
4
5
6
7
8
www.xilinx.com
Output Parallel-to-Serial Logic Resources (OSERDES)
Input Data Width Output in DDR
Mode
10
4
6
8
–
–
–
CLK
Table 8-6
2X
3X
4X
5X
6X
7X
8X
CLKDIV
describes
X
X
X
X
X
X
X
387
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