XC5VLX50T-3FF1136C Xilinx Inc, XC5VLX50T-3FF1136C Datasheet - Page 82
![IC FPGA VIRTEX-5 50K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50T-3FF1136C
Manufacturer Part Number
XC5VLX50T-3FF1136C
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50T-3FF1136C
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
122-1586 - BOARD EVAL FOR VIRTEX-5 ML555HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
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Chapter 2: Clock Management Technology
82
It is also possible to use the DCM to drive a PLL. This setup reduces the overall jitter of
both the source clock and the DCM clock output. In this case, only up to two of the DCM
output clocks can drive the PLL. Therefore, only up to two DCM clocks can access the PLL
and benefit from the reduced jitter.
Figure 2-15
illustrates the direct connection between DCM and PLL within a CMT. Only one DCM
output can drive PLL using the direct connection within a CMT without routing through a
global buffer (BUFG). The DCM and PLL can be within the same or different CMTs.
Figure 2-16
between the DCM clocks driving the PLL input clocks. The DCM and PLL can be within
the same or different CMTs. Refer to
information on PLLs.
X-Ref Target - Figure 2-15
and
illustrates two DCMs driving a PLL. In this case, BUFG must also be inserted
Figure 2-15: Direct Connection between DCM and PLL
Figure 2-16
IBUFG
www.xilinx.com
illustrate two scenarios of the DCM driving a PLL.
CLKIN1
CLKFBIN
RST
CLKIN
CLKFBIN
RST
Chapter 3, Phase-Locked Loops (PLLs)
DCM
PLL
CLKFBOUT
CLKFX180
CLK2X180
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
CLK180
CLK270
CLKDV
CLK2X
CLKFX
CLK90
CLK0
ug190_2_16_040906
BUFG
BUFG
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
for more
Figure 2-15
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