XC5VLX50T-3FF1136C Xilinx Inc, XC5VLX50T-3FF1136C Datasheet - Page 108
![IC FPGA VIRTEX-5 50K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50T-3FF1136C
Manufacturer Part Number
XC5VLX50T-3FF1136C
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50T-3FF1136C
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
122-1586 - BOARD EVAL FOR VIRTEX-5 ML555HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
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- Download datasheet (14Mb)
Chapter 3: Phase-Locked Loops (PLLs)
X-Ref Target - Figure 3-14
108
1
Matches
IBUFG
PLL Driving DCM
2
3
CLKIN1
CLKFBIN
RST
CLKIN
CLKFBIN
RST
A second option for reduce clock jitter is to use the PLL to clean-up the input clock jitter
before driving into the DCM. This will improve the output jitter of all DCM outputs, but
any added jitter by the DCM will still be passed to the clock outputs. Both PLL and DCM
should reside in the same CMT block because dedicated resources exist between the PLL
and DCM to support the zero delay mode. When the PLL and DCM do not reside in the
same CMT, then the only connection is through a BUFG hindering the possibility of
deskew.
One PLL can drive multiple DCMs as long as the reference frequency can be generated by
a single PLL. For example, if a 33 MHz reference clock is driven into the PLL, and the
design uses one DCM to operate at 200 MHz and the other to run at 100 MHz, then the
VCO can be operated at 600 MHz (M1 = 18). The VCO frequency can be divided by three to
generate a 200 MHz clock and another counter can be divided by six to generate the
100 MHz clock. For the example in
DCM
PLL
CLKFBOUT
CLKFX180
CLK2X190
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
CLK190
CLK270
CLKDV
CLKFX
CLK2X
CLK90
CLK0
Figure 3-14: PLL Driving a DCM
www.xilinx.com
BUFG
Figure
4
5
6
3-14, one PLL can drive both DCMs.
To Logic, etc.
To Logic, etc.
1
2
3
4
5
6
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ug190_3_14_092107
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