XC5VSX50T-1FFG665C Xilinx Inc, XC5VSX50T-1FFG665C Datasheet - Page 326

• Manufacturer Part Number: XC5VSX50T-1FFG665C
• Description: IC FPGA VIRTEX-5 50K 665-FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-1FFG665C

• Total Ram Bits: 4866048
• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• No. Of Logic Blocks: 8160
• No. Of Gates: 50000
• Family Type: Virtex-5 SXT
• No. Of Speed Grades: 1
• No. Of I/o's: 360
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1568

Chapter 7: SelectIO Logic Resources
Table 7-6: IODELAY Configurations Supported
326
IDELAY
ODELAY
Bidirectional
Delay
IODELAY
Mode
IODELAY Primitive
O (when T = 0) ODATAIN OLOGIC/OSERDES OBUF
I (when T = 1)
Direction of
IODELAY
O
I
•
Figure 7-6
Figure 7-8
X-Ref Target - Figure 7-8
Table 7-7
Table 7-7: IODELAY Primitive Ports
DATAOUT
ODATAIN
IDATAIN
Variable IDELAY (IDELAY_TYPE = VARIABLE) and fixed ODELAY mode
In this mode, only the IDELAY value can be dynamically changed after configuration
by manipulating the control signals CE and INC. The logic level of the T pin in the
IODELAY primitive dynamically determines if the block is in IDELAY or ODELAY
mode. When used in this mode, the IDELAYCTRL primitive must be instantiated. See
IDELAYCTRL Usage and Design Guidelines
Name
Port
Used in the
ODATAIN OLOGIC/OSERDES OBUF
Input Pin
IODELAY
IDATAIN
IDATAIN
Element
DATAIN
lists the available ports in the IODELAY primitive. All ports are 1-bit wide.
lists the supported IODELAY configurations.
shows the IODELAY primitive.
Direction
IBUF
Fabric
IBUF
Output
Input
Input
ODATAIN
IDATAIN
DATAIN
Source
RST
INC
www.xilinx.com
CE
C
T
Figure 7-8: IODELAY Primitive
Delayed data from one of three data input ports (IDATAIN,
ODATAIN, DATAIN)
Data input for IODELAY from the IOB.
Data input for IODELAY from the OSERDES/OLOGIC
ILOGIC/ISERDES/Fabric Default/Fixed/Variable
ILOGIC/ISERDES/Fabric Fixed/Variable
IODELAY
Destination
for more details.
Function
ug190_7_08_041106
DATAOUT
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Supported Delay Modes
Fixed/Variable
Fixed
Fixed