XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 392

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 8: Advanced SelectIO Logic Resources
392
OSERDES Width Expansion
DATA_RATE_TQ Attribute
DATA_WIDTH Attribute
SERDES_MODE Attribute
TRISTATE_WIDTH Attribute
The DATA_RATE_TQ attribute defines whether 3-state control is to be processed as single
data rate (SDR) or double data rate (DDR). The allowed values for this attribute are SDR
and DDR. The default value is DDR.
The DATA_WIDTH attribute defines the parallel data input width of the parallel-to-serial
converter. The possible values for this attribute depend on the DATA_RATE_OQ attribute.
When DATA_RATE_OQ is set to SDR, the possible values for the DATA_WIDTH attribute
are 2, 3, 4, 5, 6, 7, and 8. When DATA_RATE_OQ is set to DDR, the possible values for the
DATA_WIDTH attribute are 4, 6, 8, and 10.
When the DATA_WIDTH is set to widths larger than six, a pair of OSERDES must be
configured into a master-slave configuration, and the DATA_WIDTH value of both
OSERDES must be set to the desired width. For example, for a width of 8, both MASTER
and SLAVE must have DATA_WIDTH set to 8. See
The SERDES_MODE attribute defines whether the OSERDES module is a master or slave
when using width expansion. The possible values are MASTER and SLAVE. The default
value is MASTER. See
The TRISTATE_WIDTH attribute defines the parallel 3-state input width of the 3-state
control parallel-to-serial converter. The possible values for this attribute depend on the
DATA_RATE_TQ attribute. When DATA_RATE_TQ is set to SDR or BUF, the
TRISTATE_WIDTH attribute can only be set to 1. When DATA_RATE_TQ is set to DDR,
the possible values for the TRISTATE_WIDTH attribute are 2 or 4.
TRISTATE_WIDTH cannot be set to widths larger than four. The TRISTATE_WIDTH and
DATA_RATE_TQ attribute settings do not impose any limits on the DATA_RATE_OQ and
DATA_WIDTH settings, except when TRISTATE_WIDTH is set to 4 and DATA_RATE_TQ
is set to DDR. In this case, the only allowable DATA_RATE_OQ and DATA_WIDTH
settings are:
Two OSERDES modules are used to build a parallel-to-serial converter larger than 6:1. In
every I/O tile there are two OSERDES modules; one master and one slave. By connecting
the SHIFTIN ports of the master OSERDES to the SHIFTOUT ports of the slave OSERDES,
the parallel-to-serial converter can be expanded to up to 10:1(DDR) and 8:1 (SDR).
If the output is differential, the master OSERDES must be on the positive side of the
differential output pair. If the output is not differential, the output buffer associated with
the slave OSERDES is not available for use.
Complementary single-ended standards (e.g., DIFF_HSTL, DIFF_SSTL) cannot be used
when using the OSERDES with width expansion. This is because the complementary
single-ended standards use both OLOGIC blocks in an I/O tile to transmit both legs of the
signal, leaving no OLOGIC blocks to use for width expansion.
DATA_RATE_OQ =DDR; DATA_WIDTH = 4
DATA_RATE_OQ = SDR; DATA_WIDTH = 2
“OSERDES Width
www.xilinx.com
Expansion”.
“OSERDES Width
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
Expansion”.
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